Substrate integrated transmission lines: Review and applications
This paper presents a general overview of substrate integrated transmission lines, from the
perspective of historical background and progress of guided-wave structures and their …
perspective of historical background and progress of guided-wave structures and their …
DRAMsim3: A cycle-accurate, thermal-capable DRAM simulator
DRAM technology has developed rapidly in recent years. Several industrial solutions offer
3D packaging of DRAM and some are envisioning the integration of CPU and DRAM on the …
3D packaging of DRAM and some are envisioning the integration of CPU and DRAM on the …
Large-scale 3D chips: Challenges and solutions for design automation, testing, and trustworthy integration
Three-dimensional (3D) integration of electronic chips has been advocated by both industry
and academia for many years. It is acknowledged as one of the most promising approaches …
and academia for many years. It is acknowledged as one of the most promising approaches …
Bandwidth-Effective DRAM Cache for GPU s with Storage-Class Memory
We propose overcoming the memory capacity limitation of GPUs with high-capacity Storage-
Class Memory (SCM) and DRAM cache. By significantly increasing the memory capacity …
Class Memory (SCM) and DRAM cache. By significantly increasing the memory capacity …
Efficient Thermal-Stress Coupling Design of Chiplet-Based System with Coaxial TSV Array
In this research, an efficient thermal-stress coupling design method for a Chiplet-based
system with a coaxial through silicon via (CTSV) array is developed by combining the …
system with a coaxial through silicon via (CTSV) array is developed by combining the …
Machine learning based effective linear regression model for TSV layer assignment in 3DIC
On the integration of 3D IC design, thermal management issues play a significant role. So, it
is required to implement an effective approaches and solutions for integrating 3DIC. The …
is required to implement an effective approaches and solutions for integrating 3DIC. The …
Optimization of thermal aware multilevel routing for 3D IC
Due to the technological advancements, the three dimensional Integrated Circuits become
the most popular technology. But it has the major drawback of increased time consumption …
the most popular technology. But it has the major drawback of increased time consumption …
AdEle+: An Adaptive Congestion-and-Energy-Aware Elevator Selection for Partially Connected 3D Networks-on-Chip
Vertical die stacking of 3D Networks-on-Chip (3D NoCs) is enabled using inter-layer
Through-Silicon-Via (TSV) links. However, TSV technology suffers from low reliability and …
Through-Silicon-Via (TSV) links. However, TSV technology suffers from low reliability and …
Optimal die placement for interposer-based 3D ICs
Performance of modern multi-chip modules, increasingly implemented as interposer
solutions, is limited by system-level interconnects. We propose an effective method for …
solutions, is limited by system-level interconnects. We propose an effective method for …
Time-domain power distribution network (PDN) analysis for 3-D integrated circuits based on WLP-FDTD
In this article, a new efficient unconditionally stable time-domain modeling algorithm based
on the weighted Laguerre polynomial finite-difference time-domain (WLP-FDTD) method is …
on the weighted Laguerre polynomial finite-difference time-domain (WLP-FDTD) method is …