HERMES: an infrastructure for low area overhead packet-switching networks on chip
The increasing complexity of integrated circuits drives the research of new on-chip
interconnection architectures. A network on chip draws on concepts inherited from …
interconnection architectures. A network on chip draws on concepts inherited from …
NoC routing protocols–objective-based classification
AB Gabis, M Koudil - Journal of Systems Architecture, 2016 - Elsevier
Abstract NoCs (Network on Chips) are the most popular interconnection mechanism used
for systems that require flexibility, extensibility and low power consumption. However …
for systems that require flexibility, extensibility and low power consumption. However …
[图书][B] On-chip communication architectures: system on chip interconnect
S Pasricha, N Dutt - 2010 - books.google.com
Over the past decade, system-on-chip (SoC) designs have evolved to address the ever
increasing complexity of applications, fueled by the era of digital convergence …
increasing complexity of applications, fueled by the era of digital convergence …
Argo: A real-time network-on-chip architecture with an efficient GALS implementation
In this paper, we present an area-efficient, globally asynchronous, locally synchronous
network-on-chip (NoC) architecture for a hard real-time multiprocessor platform. The NoC …
network-on-chip (NoC) architecture for a hard real-time multiprocessor platform. The NoC …
[图书][B] Design of cost-efficient interconnect processing units: Spidergon STNoC
M Coppola, MD Grammatikakis, R Locatelli… - 2020 - taylorfrancis.com
Streamlined Design Solutions Specifically for NoCTo solve critical network-on-chip (NoC)
architecture and design problems related to structure, performance and modularity …
architecture and design problems related to structure, performance and modularity …
[PDF][PDF] Evaluation of routing algorithms on mesh based nocs
The increasing complexity of integrated circuits drives the research of new on-chip
interconnection architectures. Networks-on-chip (NoCs) are a candidate architecture to be …
interconnection architectures. Networks-on-chip (NoCs) are a candidate architecture to be …
LiPaR: A light-weight parallel router for FPGA-based networks-on-chip
B Sethuraman, P Bhattacharya, J Khan… - Proceedings of the 15th …, 2005 - dl.acm.org
Present day technology for ASICs supports Networks-on-Chip designs which can have 100
million gates on a single chip. The latest FPGAs can support only about 10 million gates to …
million gates on a single chip. The latest FPGAs can support only about 10 million gates to …
Low‐cost regional‐based congestion‐aware routing algorithm for 2D mesh NoC
Given the advantages of network‐on‐chips (NoCs), they are rapidly improving to replace
other forms of System‐on‐Chip (SoC) designs. Although various factors improve the NoC's …
other forms of System‐on‐Chip (SoC) designs. Although various factors improve the NoC's …
optiMap: a tool for automated generation of NoC architectures using multi-port routers for FPGAs
B Sethuraman, R Vemuri - … of the Design Automation & Test in …, 2006 - ieeexplore.ieee.org
Networks-on-chip (NoC) way of system design has been introduced to overcome the
communication and the performance bottlenecks of a bus based system design. Area is at a …
communication and the performance bottlenecks of a bus based system design. Area is at a …
A segmented adaptive router for near energy-proportional networks-on-chip
A Network-on-Chip (NoC) is an essential component of a chip multiprocessor (CMP) which
however contributes to a large fraction of system energy. The unpredictability of traffic across …
however contributes to a large fraction of system energy. The unpredictability of traffic across …