This paper presents a novel all-digital CDR scheme in 90 nm CMOS. Two independently
adjustable clock phases are generated from a delay line calibrated to 2 UI. One clock phase …

This study provides a comprehensive review of decision feedback equalisation (DFE) for
multi‐giga‐bit‐per‐second (Gbps) data links. The state‐of‐the‐art of DFE for multi‐Gbps …

This paper describes a 28-Gb/s receiver IC with self-contained adaptive equalization and
sampling point control using an on-chip stochastic sigma-tracking eye-opening monitor …

This paper presents a digital-to-phase converter (DPC) with 8-bits of resolution and a wide
frequency range for the input/output clocks. A harmonic rejection (HR) filter is introduced to …

This work focuses on the basic signal integrity issues of high-speed wireline links. It bridges
the gap between optimum system design and circuit design for such links by:(1) …

Due to the lack of widely applicable fault models, testing for analog, mixedsignal (AMS), and
radio frequency (RF) circuits has been, and will continue to be, primarily based on checking …

A 10-Gb/s on-chip 1-D eye-opening monitor (EOM) for receiver front-end equalizer boost
gain adaptations is presented. The proposed EOM circuits report in real-time horizontal eye …

A loop gain adaptation technique is proposed, which optimizes the jitter tolerance (JTOL) of
a 28 Gb/s phase interpolator (PI)-based clock and data recovery (CDR) circuit implemented …

40-Gb/s clock and data recovery (CDR) circuit with an integrated high-precision eye-
opening monitor (EOM) circuit and an adaptive control scheme for optimizing the data …

Based on four-level pulse-amplitude modulation (PAM-4) symbol transition, this study
investigated a two-dimensional (2D) symbol map** technique that evaluates the quality of …