A review of yield modelling techniques for semiconductor manufacturing

N Kumar, K Kennedy, K Gildersleeve… - … Journal of Production …, 2006 - Taylor & Francis
Semiconductor manufacturing is a complex multistage manufacturing process, and wafer
fabs use complex processes involving billions of dollars worth of equipment to produce …

[BUCH][B] VLSI test principles and architectures: design for testability

LT Wang, CW Wu, X Wen - 2006 - books.google.com
This book is a comprehensive guide to new DFT methods that will show the readers how to
design a testable and quality product, drive down test cost, improve product quality and …

[PDF][PDF] Autonomic restoration of electrical conductivity

BJ Blaiszik, SLB Kramer, ME Grady… - Advanced …, 2012 - autonomic.beckman.illinois.edu
Figure 1. Autonomic conductivity restoration concept in a multilayer microelectronic device.
a) The self-healing circuit consists of microencapsulated liquid metal dispersed in a …

AI/ML algorithms and applications in VLSI design and technology

D Amuru, A Zahra, HV Vudumula, PK Cherupally… - Integration, 2023 - Elsevier
An evident challenge ahead for the integrated circuit (IC) industry is the investigation and
development of methods to reduce the design complexity ensuing from growing process …

Coverage directed test generation for functional verification using bayesian networks

S Fine, A Ziv - Proceedings of the 40th annual Design Automation …, 2003 - dl.acm.org
Functional verification is widely acknowledged as the bottleneck in the hardware design
cycle. This paper addresses one of the main challenges of simulation based verification (or …

[BUCH][B] System-on-chip test architectures: nanometer design for testability

LT Wang, CE Stroud, NA Touba - 2010 - books.google.com
Modern electronics testing has a legacy of more than 40 years. The introduction of new
technologies, especially nanometer technologies with 90nm or smaller geometry, has …

Exploiting structural duplication for lifetime reliability enhancement

J Srinivasan, SV Adve, P Bose… - … Architecture (ISCA'05), 2005 - ieeexplore.ieee.org
Increased power densities (and resultant temperatures) and other effects of device scaling
are predicted to cause significant lifetime reliability problems in the near future. In this paper …

[PDF][PDF] Roadmap for nanoelectronics

R Compano, L Molenkamp, DJ Paul - European Commission IST …, 2000 - researchgate.net
A “Roadmap” is an extended look at the future of a chosen field of inquiry composed from
the collective knowledge of researchers in that field. The composition of a roadmap can …

[BUCH][B] Digital microfluidic biochips: synthesis, testing, and reconfiguration techniques

K Chakrabarty, F Su - 2018 - taylorfrancis.com
Digital Microfluidic Biochips focuses on the automated design and production of microfluidic-
based biochips for large-scale bioassays and safety-critical applications. Bridging areas of …

A process-tolerant cache architecture for improved yield in nanoscale technologies

A Agarwal, BC Paul, H Mahmoodi… - IEEE Transactions on …, 2005 - ieeexplore.ieee.org
Process parameter variations are expected to be significantly high in a sub-50-nm
technology regime, which can severely affect the yield, unless very conservative design …