A novel high speed & power efficient half adder design using MTCMOS Technique in 45 nanometre regime
S Akashe, NK Tiwari, J Shrivas… - 2012 IEEE international …, 2012 - ieeexplore.ieee.org
A novel high speed low power half adder cell is proposed in this paper. The critical path
consist of an AND gate and an EX-OR gate. This cell offers higher speed, lower power …
consist of an AND gate and an EX-OR gate. This cell offers higher speed, lower power …
[PDF][PDF] A low power high speed adders using MTCMOS Technique
Addition is the most basic arithmetic operation and adder is the most fundamental arithmetic
component of the processor. Two important attributes of all digital circuits, for most …
component of the processor. Two important attributes of all digital circuits, for most …
Performance and analysis of 10T Full Adder using MTCMOS technique
V Agarawal, R Shrivastava… - 2015 International …, 2015 - ieeexplore.ieee.org
Full Adder performs addition and therefore in microprocessor and digital signal processor, it
is used for arithmetic operation, for comparison and for access the address in memory …
is used for arithmetic operation, for comparison and for access the address in memory …
[PDF][PDF] High performance and low power 8 bit 16t full adder using mtcmos technique
NS JasbirKaur - International Journal of Engineering Development and …, 2017 - rjwave.org
The most fundamental operation of any processor is the addition. For any circuit there are
two important parameters that comes into count is high speed and low power consumption …
two important parameters that comes into count is high speed and low power consumption …
Standby and active leakage current control mechanism of half adder cell
P Kushwah, S Akashe - … on Power, Energy and Controls with …, 2014 - ieeexplore.ieee.org
The proposed paper shows the half adder circuit with low power consumption preferred for
arithmetic operations. Leakage power dissipation problem of electronics systems has …
arithmetic operations. Leakage power dissipation problem of electronics systems has …
Implementation of 2: 4 DECODER for low leakage Using MTCMOS Technique in 45 Nanometre Regime
A newly high performance and low leakage 2: 4 decoder is proposed in this paper. We are
compare the MTCMOS techniques (Multi Threshold Complementary Metal Oxide …
compare the MTCMOS techniques (Multi Threshold Complementary Metal Oxide …
[PDF][PDF] Power Efficiency of Half Adder Design Using MTCMOS Technique in 35 Nanometre Regime.
PS Yadav, VK Pandey - … Journal for Innovative Research in Science …, 2015 - academia.edu
A novel high speed low power half adder cell is proposed in this paper. The critical path
consist of an AND gate and an EX-OR gate. This cell offers higher speed, lower power …
consist of an AND gate and an EX-OR gate. This cell offers higher speed, lower power …
High Performance and Low Power 8 bit 16T full adder using MTCMOS Technique
N Singla - INTERNATIONAL JOURNAL OF ENGINEERING …, 2017 - rjwave.org
The most fundamental operation of any processor is the addition. For any circuit there are
two important parameters that comes into count is high speed and low power consumption …
two important parameters that comes into count is high speed and low power consumption …
[PDF][PDF] Design low power SRAM using MTCMOS Technique with Nanometer Regime
A Tiwari, R Singh - Intl J Engg Sci Adv Research, 2016 - ramauniversityjournal.com
In this paper proposed to new high performance SRAM Cell with the help of MTCMOS
Techniques. This paper represents the simulation of 6T SRAM cells using low power …
Techniques. This paper represents the simulation of 6T SRAM cells using low power …
[PDF][PDF] Design and Analysis of Multi-Threshold CMOS 14T Full Adder using 180nm
In nanometer regime, the stand by leakage power and ground bounce noise are becoming
most important parameter to kept in consideration are compactness and power which affects …
most important parameter to kept in consideration are compactness and power which affects …