Managing GPU concurrency in heterogeneous architectures
Heterogeneous architectures consisting of general-purpose CPUs and throughput-
optimized GPUs are projected to be the dominant computing platforms for many classes of …
optimized GPUs are projected to be the dominant computing platforms for many classes of …
Self-optimizing and self-programming computing systems: A combined compiler, complex networks, and machine learning approach
There exists an urgent need for determining the right amount and type of specialization
while making a heterogeneous system as programmable and flexible as possible …
while making a heterogeneous system as programmable and flexible as possible …
On-chip communication network for efficient training of deep convolutional networks on heterogeneous manycore systems
Convolutional Neural Networks (CNNs) have shown a great deal of success in diverse
application domains including computer vision, speech recognition, and natural language …
application domains including computer vision, speech recognition, and natural language …
Learning-based application-agnostic 3D NoC design for heterogeneous manycore systems
The rising use of deep learning and other big-data algorithms has led to an increasing
demand for hardware platforms that are computationally powerful, yet energy-efficient. Due …
demand for hardware platforms that are computationally powerful, yet energy-efficient. Due …
OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures
As we integrate data-parallel GPUs with general-purpose CPUs on a single chip, the
enormous cache traffic generated by GPUs will not only exhaust the limited cache capacity …
enormous cache traffic generated by GPUs will not only exhaust the limited cache capacity …
Hybrid network-on-chip architectures for accelerating deep learning kernels on heterogeneous manycore platforms
In recent years, designing specialized manycore heterogeneous architectures for deep
learning kernels has become an area of great interest. However, the typical on-chip …
learning kernels has become an area of great interest. However, the typical on-chip …
Extending the power-efficiency and performance of photonic interconnects for heterogeneous multicores with machine learning
S Van Winkle, AK Kodi, R Bunescu… - 2018 IEEE International …, 2018 - ieeexplore.ieee.org
As communication energy exceeds computation energy in future technologies, traditional on-
chip electrical interconnects face fundamental challenges in the many-core era. Photonic …
chip electrical interconnects face fundamental challenges in the many-core era. Photonic …
Leveraging silicon-photonic noc for designing scalable gpus
Silicon-photonic link technology promises to satisfy the growing need for high bandwidth,
low-latency and energy-efficient network-on-chip (NoC) architectures. While silicon-photonic …
low-latency and energy-efficient network-on-chip (NoC) architectures. While silicon-photonic …
A survey of architectural approaches for improving GPGPU performance, programmability and heterogeneity
With the skyrocketing advances of process technology, the increased need to process huge
amount of data, and the pivotal need for power efficiency, the usage of Graphics Processing …
amount of data, and the pivotal need for power efficiency, the usage of Graphics Processing …
HyWin: Hybrid wireless NoC with sandboxed sub-networks for CPU/GPU architectures
Heterogeneous System Architectures (HSA) that integrate cores of different architectures
(CPU, GPU, etc.) on single chip are gaining significance for many class of applications to …
(CPU, GPU, etc.) on single chip are gaining significance for many class of applications to …