High performance FPGA based secured hardware model for IoT devices

A Shrivastava, D Haripriya, YD Borole, A Nanoty… - International Journal of …, 2022 - Springer
Data transmission is always vulnerable to assault on the digital side. Cipher strength
analysis is a crucial component of a business or academic safety evaluation. For data …

High throughput and area‐efficient FPGA implementation of AES for high‐traffic applications

K Shahbazi, SB Ko - IET Computers & Digital Techniques, 2020 - Wiley Online Library
This study presents a high throughput field‐programmable gate array (FPGA)
implementation of advanced encryption standard‐128 (AES‐128). AES is a well‐known …

Design and implementation of advanced encryption standard algorithm on 7th series field programmable gate array

P **dal, A Kaushik, K Kumar - 2020 7th international …, 2020 - ieeexplore.ieee.org
Transmission of data digitally is always susceptible to attacks. Analysis of cipher strength is
a necessary part of the protection assessment of either corporate or academic institutions …

Enhanced AES cryptosystem by using genetic algorithm and neural network in S-box

K Kalaiselvi, A Kumar - 2016 IEEE International Conference on …, 2016 - ieeexplore.ieee.org
Cryptography based on block ciphers use Key-dependent ciphers for encryption and
decryption. The efficiency of these systems depends on the security and the speed of the …

Efficient implementations for AES encryption and decryption

RR Rachh, PVA Mohan, BS Anami - Circuits, Systems, and Signal …, 2012 - Springer
This paper proposes two efficient architectures for hardware implementation of the
Advanced Encryption Standard (AES) algorithm. The composite field arithmetic for …

Composite field arithematic based s-box for aes algorithm

SV Gaded, A Deshpande - 2019 3rd International conference …, 2019 - ieeexplore.ieee.org
Generally AES algorithm uses Substitution box which works with ROM based lookup tables.
Using the rom based Look up table, there occurs a significant irreducible amount of delay in …

[PDF][PDF] Implementation of an optimized and pipelined combinational logic rijndael S-Box on FPGA

B Rashidi, B Rashidi - IJ Computer Network and Information Security, 2013 - academia.edu
In this paper, presents an optimized combinational logic based Rijndael S-Box
implementation for the SubByte transformation (S-box) in the Advanced Encryption Standard …

Digital image encryption implementations based on AES algorithm

A AlRababah - VAWKUM Transactions on Computer Sciences, 2017 - vfast.org
Objectives: To increase needed for exchanging digital photos electronically, due to alarming
demand for multimedia applications, and because of the increasing use of images in …

VLSI design of a reconfigurable S-box based on memory sharing method

W Shan, X Zhang, X Fu, P Cao - IEICE Electronics Express, 2014 - jstage.jst.go.jp
S-box is a core component of many block cipher algorithms. A reconfigurable S-box based
on look-up table (LUT) with memory-sharing is proposed in this paper. It uses a sharing …

A secure Data Hiding Scheme Using LFSR and Modified AES

S Chakraborty, P Biswas, N Kar - 2024 IEEE 9th International …, 2024 - ieeexplore.ieee.org
In the realm of cyberspace, the requirement for data confidentiality is of utmost importance
and cannot be overlooked. To effectively address this concern, the proposed work aims to …