Three dimensional memory device containing multilayer wordline barrier films and method of making thereof
R Sharangpani, F Amano, RS Makala, F Zhou… - US Patent …, 2019 - Google Patents
Memory stack structures are formed through an alternating stack of insulating layers and
sacrificial material layers. Backside recesses are formed by removal of the sacrificial …
sacrificial material layers. Backside recesses are formed by removal of the sacrificial …
Three-dimensional memory device with amorphous barrier layer and method of making thereof
R Sharangpani, RS Makala, K Shukla, F Zhou… - US Patent …, 2019 - Google Patents
Memory stack structures are formed through an alternating stack of insulating layers and
sacrificial material layers. Backside recesses are formed by removal of the sacrificial …
sacrificial material layers. Backside recesses are formed by removal of the sacrificial …
Semiconductor devices
JJ Kim, DS Lee, SY Kim, JK Jang, W Chung… - US Patent …, 2019 - Google Patents
ABSTRACT A semiconductor device includes a first transistor having a first threshold
voltage, and including first channels, first source/drain layers connected to opposite …
voltage, and including first channels, first source/drain layers connected to opposite …
Semiconductor devices and methods of fabricating the same
MK Park, JY Song, H Na, YT Hwang, K Yoon… - US Patent …, 2019 - Google Patents
Semiconductor device having less defects in a gate insulat ing film and improved reliability
and methods of forming the semiconductor devices are provided. The semiconductor …
and methods of forming the semiconductor devices are provided. The semiconductor …
Semiconductor device having multiwork function gate patterns
M Park, NA Hoonjoo, J Song, S Hyun - US Patent 9,786,759, 2017 - Google Patents
(57) ABSTRACT A semiconductor device includes a semiconductor substrate having a first
area and a second area, and a first gate pattern on the first area and a second gate pattern …
area and a second area, and a first gate pattern on the first area and a second gate pattern …
Semiconductor device including work function adjusting metal gate structure
BH Lee, WD Kim, JH Park, SJ Hyun - US Patent 11,282,939, 2022 - Google Patents
(57) ABSTRACT A semiconductor device is provided. The semiconductor device comprising
a multi-channel active pattern on a sub strate, a high dielectric constant insulating layer …
a multi-channel active pattern on a sub strate, a high dielectric constant insulating layer …
Semiconductor devices
W Chung, JJ Kim, J Jang, S Kim, NA Hoonjoo… - US Patent …, 2019 - Google Patents
A semiconductor device includes first semiconductor patterns vertically stacked on a
substrate and vertically spaced apart from each other, and a first gate electrode on the first …
substrate and vertically spaced apart from each other, and a first gate electrode on the first …
Field effect transistors having multiple effective work functions
Selective deposition of a silicon-germanium surface layer on semiconductor surfaces can be
employed to provide two types of channel regions for field effect transistors. Anneal of an …
employed to provide two types of channel regions for field effect transistors. Anneal of an …
FinFET and fabricating method thereof
CT Lin, WT Chiang - US Patent 9,159,626, 2015 - Google Patents
A fin-shaped field-effect transistor process includes the following steps. A substrate is
provided. A first fin-shaped field-effect transistor and a second fin-shaped field-effect …
provided. A first fin-shaped field-effect transistor and a second fin-shaped field-effect …
Gate structure, fin field-effect transistor, and method of manufacturing fin-field effect transistor
JC Chen, CH Su, KT Liu, SH Chiu - US Patent 11,270,994, 2022 - Google Patents
A gate structure includes a gate dielectric layer, a work function layer, a metal layer, and a
barrier layer. The work function layer is on the gate dielectric layer. The metal layer is over …
barrier layer. The work function layer is on the gate dielectric layer. The metal layer is over …