Capacitor-less dynamic random access memory based on a III–V transistor with a gate length of 14 nm
Dynamic random access memory (DRAM) cells are commonly used in electronic devices
and are formed from a single transistor and capacitor. Alternative approaches, which are …
and are formed from a single transistor and capacitor. Alternative approaches, which are …
Performance improvement of 1T DRAM by raised source and drain engineering
In this work, a double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET)
with raised source and drain (RSD) regions is utilized for application of one-transistor (1T) …
with raised source and drain (RSD) regions is utilized for application of one-transistor (1T) …
Revisiting row hammer: A deep dive into understanding and resolving the issue
H Wang, X Peng, Z Liu, X Huang, T Li, B Yang… - Microelectronics …, 2024 - Elsevier
Row hammer is a vulnerability in Dynamic Random Access Memory (DRAM) chips, whereby
repeatedly accessing a specific row in the DRAM chip may cause bit flips in memory cells …
repeatedly accessing a specific row in the DRAM chip may cause bit flips in memory cells …
A review of sharp-switching band-modulation devices
This paper reviews the recently-developed class of band-modulation devices, born from the
recent progress in fully-depleted silicon-on-insulator (FD-SOI) and other ultrathin-body …
recent progress in fully-depleted silicon-on-insulator (FD-SOI) and other ultrathin-body …
[HTML][HTML] Performance of FDSOI double-gate dual-doped reconfigurable FETs
In this work, the electrical performance of a novel reprogrammable FDSOI device with dual-
do** at source/drain and only two top gates is investigated through advanced 3D TCAD …
do** at source/drain and only two top gates is investigated through advanced 3D TCAD …
Effects of interface states on electrical characteristics of feedback field-effect transistors
J Jeon, K Cho, S Kim - IEEE Access, 2023 - ieeexplore.ieee.org
In this study, we examine the effect of interface trap states on the electrical characteristics of
single-gated feedback field-effect transistors (FBFETs) using a commercially available …
single-gated feedback field-effect transistors (FBFETs) using a commercially available …
Simulation studies on electrical characteristics of silicon nanowire feedback field-effect transistors with interface trap charges
Y Yang, YS Park, J Son, K Cho, S Kim - Scientific reports, 2021 - nature.com
In this study, we examine the electrical characteristics of silicon nanowire feedback field-
effect transistors (FBFETs) with interface trap charges between the channel and gate oxide …
effect transistors (FBFETs) with interface trap charges between the channel and gate oxide …
Dual PN source/drain reconfigurable FET for fast and low-voltage reprogrammable logic
Schottky junction reconfigurable FETs suffer from limited output currents to drive the
following stages, jeopardizing their viability for high-end applications. This drawback …
following stages, jeopardizing their viability for high-end applications. This drawback …
Memory Operation of Z²-FET Without Selector at High Temperature
The electrical performance of Z 2-FET and memory operations of matrix are demonstrated at
high temperatures up to 125° C. The sharp subthreshold slope is maintained and the …
high temperatures up to 125° C. The sharp subthreshold slope is maintained and the …
An overview of FinFET-based capacitorless 1T-DRAM
M Rathi, GP Mishra - Device Circuit Co-Design Issues in FETs, 2023 - taylorfrancis.com
The demand for memory is increasing day by day, and the downscaling of conventional 1T-
1C DRAM in sub-10 nm technology is becoming a topic of concern. The fabrication and …
1C DRAM in sub-10 nm technology is becoming a topic of concern. The fabrication and …