Toward Ultra-Power-Efficient, Tbps Wireless Systems via Analogue Processing: Existing Approaches, Challenges and Way Forward

MM Kiasaraei, K Nikitopoulos… - … Surveys & Tutorials, 2023 - ieeexplore.ieee.org
Exploiting ultra-wide bandwidths is a promising approach to achieve the terabits per second
(Tbps) data rates required to unlock emerging mobile applications like mobile extended …

[KNIHA][B] Implementing software defined radio

E Grayver - 2012 - books.google.com
Software Defined Radio makes wireless communications easier, more efficient, and more
reliable. This book bridges the gap between academic research and practical …

20 years of turbo coding and energy-aware design guidelines for energy-constrained wireless applications

MF Brejza, L Li, RG Maunder… - … Surveys & Tutorials, 2015 - ieeexplore.ieee.org
During the last two decades, wireless communication has been revolutionized by near-
capacity error-correcting codes (ECCs), such as turbo codes (TCs), which offer a lower bit …

Iterative decoding using stochastic computation

VC Gaudet, AC Rapley - Electronics Letters, 2003 - IET
An iterative decoding architecture based on stochastic computational elements is proposed.
Simulation results for a simple low-density parity-check code demonstrate near-optimal …

Fully parallel stochastic LDPC decoders

SS Tehrani, S Mannor, WJ Gross - IEEE Transactions on signal …, 2008 - ieeexplore.ieee.org
Stochastic decoding is a new approach to iterative decoding on graphs. This paper presents
a hardware architecture for fully parallel stochastic low-density parity-check (LDPC) …

Power reduction techniques for LDPC decoders

A Darabiha, AC Carusone… - IEEE Journal of Solid …, 2008 - ieeexplore.ieee.org
This paper investigates VLSI architectures for low-density parity-check (LDPC) decoders
amenable to low-voltage and low-power operation. First, a highly-parallel decoder …

Dynamics and performance analysis of analog iterative decoding for low-density parity-check (LDPC) codes

S Hemati, AH Banihashemi - IEEE Transactions on …, 2006 - ieeexplore.ieee.org
Conventional iterative decoding with flooding or parallel schedule can be formulated as a
fixed-point problem solved iteratively by a successive substitution (SS) method. In this paper …

A 0.18-$ muhbox m $ CMOS Analog Min-Sum Iterative Decoder for a (32, 8) Low-Density Parity-Check (LDPC) Code

S Hemati, AH Banihashemi… - IEEE Journal of Solid-State …, 2006 - ieeexplore.ieee.org
Current-mode circuits are presented for implementing analog min-sum (MS) iterative
decoders. These decoders are used to efficiently decode the best known error correcting …

A 0.35-/spl mu/m CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code

D Vogrig, A Gerosa, A Neviani, AG Amat… - IEEE Journal of Solid …, 2005 - ieeexplore.ieee.org
This work presents the design and the test results of an analog decoder for the 40-bit block
length, rate 1/3, Turbo Code defined in the UMTS standard. The prototype is fully integrated …

Low-voltage CMOS circuits for analog iterative decoders

C Winstead, N Nguyen, VC Gaudet… - IEEE Transactions on …, 2006 - ieeexplore.ieee.org
Iterative decoders, including Turbo decoders, provide near-optimal error protection for
various communication channels and storage media. CMOS analog implementations of …