Low leakage zero ground bounce noise nanoscale full adder using source biasing technique
In this paper, three techniques of source biasing is presented for reduction in leakage power
at nano scale VLSI design. First technique of source biasing used NMOS sleep transistor at …
at nano scale VLSI design. First technique of source biasing used NMOS sleep transistor at …
High stable and energy efficient emerging nanoscale CNTFET SRAM cells using circuit level low power techniques
Due to unrelenting progression of silicon technology, the power dissipation has become
important concern in nanometer regime. To limit the power consumption and to improve the …
important concern in nanometer regime. To limit the power consumption and to improve the …
Optimization of Power and Delay in VLSI Circuits using Hybrid Flip-Flop Circuit
GR Krishna, R Lorenzo - 2023 3rd International Conference On …, 2023 - ieeexplore.ieee.org
In this paper a novel master-slave (MS) hybrid flip-flop is proposed using a single-phase
clock. The proposed circuit is designed in CMOS (Complementary Metal Oxide …
clock. The proposed circuit is designed in CMOS (Complementary Metal Oxide …
Design and Analysis of 18T Master-Slave Flip-Flop Circuit
GR Krishna, R Lorenzo, S Saha - 2023 12th International …, 2023 - ieeexplore.ieee.org
A novel master-slave flip-flop is designed using 18 transistors by topological techniques.
The proposed flip-flop circuit (PFC) is compared with the existing flip-flops. Key parameters …
The proposed flip-flop circuit (PFC) is compared with the existing flip-flops. Key parameters …
Leakage Power Reduction and Stability Analysis of 5 nm Node GAA CNTFET SRAMs
In modern system-on-chips (SoCs), embedded static random access memory (SRAM) units
are vital components that facilitate on-chip memory for fast data storage and access …
are vital components that facilitate on-chip memory for fast data storage and access …
Leakage minimization in CMOS VLSI circuits: a brief review
Ever increasing demand for portable and battery-operated systems has lead to aggressive
scaling. While technology scaling facilitates faster and high performance devices, at the …
scaling. While technology scaling facilitates faster and high performance devices, at the …
[ZITATION][C] Study of Leakage Power Reduction Techniques for Low Power CMOS Logic Circuits
A Kumbha - 2018 - National Institute of Technology …