Self-timed logic design methods are developed using Threshold Combinational Reduction
(TCR) within the NULL Convention Logic (NCL) paradigm. NCL logic functions are realized …

This paper develops an ultra-low power asynchronous circuit design methodology, called
Multi-Threshold NULL Convention Logic (MTNCL), also known as Sleep Convention Logic …

This paper develops a new approach to design static threshold gates with hysteresis, based
on integrating each pair of pull-up and pull-down transistor networks into one composite …

Approaches for maximizing throughput of self-timed multiply–accumulate units (MACs) are
developed and assessed using the NULL convention logic paradigm. In this class of self …

Two versions of a reconfigurable logic element are developed for use in constructing afield-
programmable gate array NULL convention logic (NCL) field-programmable gate array …

This paper presents a design methodology incorporating multi-threshold CMOS (MTCMOS)
into delay-insensitive asynchronous circuits in order to solve the problems of the …

This paper demonstrates the performance, area and supply voltage scaling advantages of a
Differential Cascode Voltage-Switch Logic (DCVSL)-like design over previous methods for …

An Early Completion technique is developed to significantly increase the throughput of
NULL Convention self-timed digital systems without impacting latency or compromising their …

Designing asynchronous circuits by reusing existing synchronous tools has become a
promising solution to the problem of poor CAD support in asynchronous world. A …

This paper develops an ultra-low power design methodology for bit-wise pipelined
asynchronous circuits, called bit-wise MTNCL, which combines multi-threshold CMOS …