Bi-objective elite differential evolution algorithm for multivalued logic networks
In this paper, a novel algorithm called bi-objective elite differential evolution (BOEDE) is
proposed to optimize multivalued logic (MVL) networks. It is a multiobjective algorithm …
proposed to optimize multivalued logic (MVL) networks. It is a multiobjective algorithm …
Multiple-valued logic design tools
DM Miller - [1993] Proceedings of the Twenty-Third …, 1993 - ieeexplore.ieee.org
A brief overview of past progress in multiple-valued logic design is presented. The methods
are considered with respect to the likely development of multiple-valued field programmable …
are considered with respect to the likely development of multiple-valued field programmable …
[PDF][PDF] Minimization algorithms for multiple-valued programmable logic arrays
PP Tirumalai, JT Butler - IEEE Transactions on Computers, 1991 - core.ac.uk
We analyze the performance of various heuristic algorithms for minimizing realizations of
multiple-valued functions by the newly developed CCD 191 and CMOS [W] programmable …
multiple-valued functions by the newly developed CCD 191 and CMOS [W] programmable …
A Chaotic Clonal Selection Algorithm and its Application to Synthesize Multiple‐Valued Logic Functions
In this paper, a chaotic clonal selection algorithm (CCSA) is proposed to synthesize multiple‐
valued logic (MVL) functions. The MVL function is realized in a multiple‐valued sum‐of …
valued logic (MVL) functions. The MVL function is realized in a multiple‐valued sum‐of …
CMOS multiple-valued logic design. II. Function realization
AK Jain, RJ Bolton… - IEEE Transactions on …, 1993 - ieeexplore.ieee.org
For pt. I see ibid vol. 40, no. 8 p 503-14 (1993). The performance of the set of operators
proposed in pt. I is compared with existing sets of operators for the realization of multiple …
proposed in pt. I is compared with existing sets of operators for the realization of multiple …
CMOS current-mode multivalued PLAs
FJ Pelayo, A Prieto, A Lloris… - IEEE transactions on …, 1991 - ieeexplore.ieee.org
A programmable logic array (PLA) structure for implementation of multivalued combinational
and sequential systems is proposed. The PLA is integrable by using a conventional CMOS …
and sequential systems is proposed. The PLA is integrable by using a conventional CMOS …
Analysis of minimization algorithms for multiple-valued programmable logic arrays
P Tirumalai, J Butler - … of the 18th International Symposium on Multiple …, 1988 - apps.dtic.mil
We compare the performance of three heuristic algorithms 3, 6, 13 for the minimization of
sum-of-products expressions realized by the newly developed multiple-valued …
sum-of-products expressions realized by the newly developed multiple-valued …
Multiple-valued CCD circuits
JT Butler, HG Kerkhoff - Computer, 1988 - ieeexplore.ieee.org
The benefits and current state of the art of charge-coupled-device logic are examined. The
fundamentals of CCD logic operations and basic CCD configurations are presented …
fundamentals of CCD logic operations and basic CCD configurations are presented …
[PDF][PDF] HAMLET-An Expression Compiler/Optimizer for the Implementation of Heuristics to Minimize Multiple-Valued Programmable Logic Arrays.
JM Yurchak, JT Butler - ISMVL, 1990 - core.ac.uk
ABSTRACT HAMLET is a CAD tool that translates a user specification of a multiple-valued
expression into a layout of a multiple-valued programmable logic array (MVLPLA) which …
expression into a layout of a multiple-valued programmable logic array (MVLPLA) which …
[PDF][PDF] A neighborhood decoupling algorithm for truncated sum minimization
C Yang, YM Wang - 2002 - core.ac.uk
There has been considerable interest in heuristic method for minimizing multiple-valued
logic functions because exact methods are intractable. This paper describes a new heuristic …
logic functions because exact methods are intractable. This paper describes a new heuristic …