A complete dynamic power estimation model for data-paths in FPGA DSP designs
R Jevtic, C Carreras - Integration, 2012 - Elsevier
A complete model for estimating power consumption in DSP-oriented designs implemented
in FPGAs is presented. The model consists of three submodels. One is used for power …
in FPGAs is presented. The model consists of three submodels. One is used for power …
Architectural Synthesis of Fixed‐Point DSP Datapaths Using FPGAs
G Caffarena, JA López, G Leyva… - International Journal …, 2009 - Wiley Online Library
We address the automatic synthesis of DSP algorithms using FPGAs. Optimized fixed‐point
implementations are obtained by means of considering (i) a multiple wordlength …
implementations are obtained by means of considering (i) a multiple wordlength …
Wordlength optimization of fixed-point algorithms
G Caffarena - … Techniques: From Component-to Application-Level, 2022 - Springer
Approximate computing enables trading off accuracy with implementation cost for
embedded implementations of algorithms. Wordlength optimization provides a means to …
embedded implementations of algorithms. Wordlength optimization provides a means to …
Fast fixed-point optimization of DSP algorithms
In this chapter, the fast fixed-point optimization of Digital Signal Processing (DSP) algorithms
is addressed. A fast quantization noise estimator is presented. The estimator enables a …
is addressed. A fast quantization noise estimator is presented. The estimator enables a …
Architectural synthesis of DSP circuits under simultaneous error and time constraints
G Caffarena, C Carreras - … Conference on VLSI and System-on …, 2010 - ieeexplore.ieee.org
In this paper, the design tasks of wordlength optimization and architectural synthesis are
combined. The benefits in comparison to the traditional sequential application of these two …
combined. The benefits in comparison to the traditional sequential application of these two …
A fast interpolative wordlength optimization method for dsp systems
As Digital Signal Processing (DSP) systems grow in complexity, the classical simulation-
based approaches to the wordlength optimization (WLO) problem for fixed-point data …
based approaches to the wordlength optimization (WLO) problem for fixed-point data …
Precision-wise architectural synthesis of dsp circuits
G Caffarena, C Carreras - 2010 18th European Signal …, 2010 - ieeexplore.ieee.org
This paper addresses the combination of wordlength optimization and architectural
synthesis as a single design task, aiming at reducing the area of FPGA implementations …
synthesis as a single design task, aiming at reducing the area of FPGA implementations …
[BOOK][B] Efficient floating-point implementation of signal processing algorithms on reconfigurable hardware
TV Huynh - 2012 - spsc.tugraz.at
This doctoral thesis aims at optimising the floating-point implementations of signal
processing algorithms on reconfigurable hardware with respect to accuracy, hardware …
processing algorithms on reconfigurable hardware with respect to accuracy, hardware …
[PDF][PDF] Automated wordlength optimization framework for multi-source statistical interval-based analysis of nonlinear systems with control-flow structures
ES Algarabel - 2016 - oa.upm.es
UNIVERSIDAD POLITÉCNICA DE MADRID AUTOMATED WORDLENGTH OPTIMIZATION
FRAMEWORK FOR MULTI-SOURCE STATISTICAL INTERVAL-BASED ANALY Page 1 …
FRAMEWORK FOR MULTI-SOURCE STATISTICAL INTERVAL-BASED ANALY Page 1 …
Automated wordlength optimization framework for multi-source statistical interval-based analysis of nonlinear systems with control-flow structures
E Sedano Algarabel - 2016 - oa.upm.es
El uso de aritmética de punto fijo es una opción de diseño muy extendida en sistemas con
fuertes restricciones de área, consumo o rendimiento. Para producir implementaciones …
fuertes restricciones de área, consumo o rendimiento. Para producir implementaciones …