Design for manufacturability and reliability in extreme-scaling VLSI
In the last five decades, the number of transistors on a chip has increased exponentially in
accordance with the Moore's law, and the semiconductor industry has followed this law as …
accordance with the Moore's law, and the semiconductor industry has followed this law as …
Layout decomposition for triple patterning lithography
As minimum feature size and pitch spacing further scale down, triple patterning lithography
is a likely 193 nm extension along the paradigm of double patterning lithography for 14-nm …
is a likely 193 nm extension along the paradigm of double patterning lithography for 14-nm …
Understanding graphs in EDA: From shallow to deep learning
As the scale of integrated circuits keeps increasing, it is witnessed that there is a surge in the
research of electronic design automation (EDA) to make the technology node scaling …
research of electronic design automation (EDA) to make the technology node scaling …
Design for manufacturing with emerging nanolithography
In this paper, we survey key design for manufacturing issues for extreme scaling with
emerging nanolithography technologies, including double/multiple patterning lithography …
emerging nanolithography technologies, including double/multiple patterning lithography …
An efficient layout decomposition approach for triple patterning lithography
Triple Patterning Lithography (TPL) is widely recognized as a promising solution for
14/10nm technology node. In this paper, we propose an efficient layout decomposition …
14/10nm technology node. In this paper, we propose an efficient layout decomposition …
Self-aligned double patterning aware pin access and standard cell layout co-optimization
Self-Aligned Double Patterning (SADP) is being considered for use at the 10 nm technology
node and below for routing layers with pitches down to~ 50nm because it has better LER …
node and below for routing layers with pitches down to~ 50nm because it has better LER …
A predictive process design kit for three-independent-gate field-effect transistors
The Three-Independent-Gate Field-Effect Transistor (TIGFET) is a promising beyond-CMOS
technology which offers many unique properties, such as (i) dynamic control of the device …
technology which offers many unique properties, such as (i) dynamic control of the device …
Layout decomposition approaches for double patterning lithography
In double patterning lithography (DPL) layout decomposition for 45 nm and below process
nodes, two features must be assigned opposite colors (corresponding to different …
nodes, two features must be assigned opposite colors (corresponding to different …
Design rule evaluation framework using automatic cell layout generator for design technology co-optimization
This paper proposes a complete and full automation framework of evaluating design rules
(DRs) to facilitate the process of design technology co-optimization (DTCO), which is highly …
(DRs) to facilitate the process of design technology co-optimization (DTCO), which is highly …
A unified framework for simultaneous layout decomposition and mask optimization
In advanced technology nodes, layout decomposition (LD) and mask optimization (MO) are
two key stages in integrated circuit design. Due to the inconsistency of the objectives of …
two key stages in integrated circuit design. Due to the inconsistency of the objectives of …