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Techniques for fast physical synthesis
The traditional purpose of physical synthesis is to perform timing closure, ie, to create a
placed design that meets its timing specifications while also satisfying electrical, routability …
placed design that meets its timing specifications while also satisfying electrical, routability …
ECO timing optimization using spare cells
YP Chen, JW Fang, YW Chang - 2007 IEEE/ACM International …, 2007 - ieeexplore.ieee.org
We introduce in this paper a new problem of ECO timing optimization using spare-cell
rewiring and present the first work for this problem. Spare-cell rewiring is a popular …
rewiring and present the first work for this problem. Spare-cell rewiring is a popular …
Path based buffer insertion
Along with the progress of VLSI technology, buffer insertion plays an increasingly critical role
on affecting circuit design and performance. Traditional buffer insertion algorithms are …
on affecting circuit design and performance. Traditional buffer insertion algorithms are …
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost
As gate delays deem faster than wire delays for each teehnolagy generation, buffer insertion
hecomes a popular method to reduce the interconnecI delay. Several modem huffer …
hecomes a popular method to reduce the interconnecI delay. Several modem huffer …
An O (bn/sup 2/) time algorithm for optimal buffer insertion with b buffer types
Buffer insertion is a popular technique to reduce the interconnect delay. The classic buffer
insertion algorithm of van Ginneken has a time complexity of O (n/sup 2/), where n is the …
insertion algorithm of van Ginneken has a time complexity of O (n/sup 2/), where n is the …
Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random Leff variation
This paper studies the impacts of Chemical Mechanical Polishing (CMP)-induced systematic
variation and random channel length (L eff) variation of transistors on interconnect design …
variation and random channel length (L eff) variation of transistors on interconnect design …
Threshold voltage control through multiple supply voltages for power-efficient FinFET interconnects
A Muttreja, P Mishra, NK Jha - 21st International Conference on …, 2008 - ieeexplore.ieee.org
In modern circuits, interconnect efficiency is a central determinant of circuit efficiency.
Moreover, as technology is scaled down, the importance of efficient interconnect design is …
Moreover, as technology is scaled down, the importance of efficient interconnect design is …
Making fast buffer insertion even faster via approximation techniques
As technology scales to 0.13 micron and below, designs are requiring buffers to be inserted
on interconnects of even moderate length for both critical paths and fixing electrical …
on interconnects of even moderate length for both critical paths and fixing electrical …
A fast algorithm for identifying good buffer insertion candidate locations
Van Ginneken's algorithm [18] for performing buffer insertion is a classic in the field, since it
optimally solves the problem subject to a set of fixed buffer insertion candidate locations for …
optimally solves the problem subject to a set of fixed buffer insertion candidate locations for …
Hybrid broadcast-unicast distribution of mobile TV over 3G networks
T Lohmar, U Horn - … . 2006 31st IEEE Conference on Local …, 2006 - ieeexplore.ieee.org
Several mobile operators have already launched MobileTV services in their network.
Although traditionally delivered over broadcast those services are delivered over uni-cast …
Although traditionally delivered over broadcast those services are delivered over uni-cast …