Comprehensive survey of ternary full adders: Statistics, corrections, and assessments
S Nemati, M Haghi Kashani… - IET Circuits, Devices & …, 2023 - Wiley Online Library
The history of ternary adders goes back to more than 6 decades ago. Since then, a multitude
of ternary full adders (TFAs) have been presented in the literature. This article conducts a …
of ternary full adders (TFAs) have been presented in the literature. This article conducts a …
A logic synthesis methodology for low-power ternary logic circuits
We propose a logic synthesis methodology with a novel low-power circuit structure for
ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic …
ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic …
A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM
AS Vidhyadharan, S Vidhyadharan - Microelectronics Journal, 2021 - Elsevier
This paper presents a CNTFET based ultra-low-power ternary SRAM design which
consumes merely 66 nW of power, achieving 84–98% reduction in power consumption as …
consumes merely 66 nW of power, achieving 84–98% reduction in power consumption as …
An efficient ultra-low-power and superior performance design of ternary half adder using CNFET and gate-overlap TFET devices
S Vidhyadharan, SS Dan - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
This paper presents a novel ultra-low power yet high-performance device and circuit design
paradigm for implementing ternary logic based circuits using Gate-Overlap Tunnel FETs …
paradigm for implementing ternary logic based circuits using Gate-Overlap Tunnel FETs …
Exploration of ternary logic using T-CMOS for circuit-level design
J Ko, J Kim, T Jeong, J Jeong… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
The predicted end of scaling and the exponential increase of user data in the era of the
connected world are asking whether the current binary systems in CMOS can successfully …
connected world are asking whether the current binary systems in CMOS can successfully …
Optimizing ternary multiplier design with fast ternary adder
Existing ternary multiplier designs are difficult to use in ternary systems. Thus, ternary
Wallace tree multipliers that reduce the number of transistors by using 4-input ternary adders …
Wallace tree multipliers that reduce the number of transistors by using 4-input ternary adders …
Pair-wise Urdhava-Tiryagbhyam (UT) vedic ternary multiplier
Multiplier acts as a central building block for most digital computations, hence is of major
significance and concern in improving speed-power-reliability in digital processing systems …
significance and concern in improving speed-power-reliability in digital processing systems …
DPL-based novel time equalized CMOS ternary-to-binary converter
ABSTRACT Radix-3 (Ternary) logic has been receiving renewed attention as a feasible
alternative to conventional Radix-2 system in processor-design and multi-valued logic …
alternative to conventional Radix-2 system in processor-design and multi-valued logic …
An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder
AS Vidhyadharan, S Vidhyadharan - Microelectronics Journal, 2021 - Elsevier
This paper presents an ultra-low-power ternary dynamic Half Adder (HA) design which
consumes merely 83 nW of power, achieving a 66–90% reduction in power consumption as …
consumes merely 83 nW of power, achieving a 66–90% reduction in power consumption as …
VLSI design of APT-VDF using novel variable block sized ternary adder and multiplier
Nowadays, Variable digital filters (VDF) play an essential role in the field of communication
and signal processing. The desired frequency response of any prototype filter can be …
and signal processing. The desired frequency response of any prototype filter can be …