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A review on SEU mitigation techniques for FPGA configuration memory
Single event upset (SEU) has become one of the major threats to dependable application
development targeted at safety systems in field programmable gate arrays (FPGAs). This …
development targeted at safety systems in field programmable gate arrays (FPGAs). This …
Improving part based object detection by unsupervised, online boosting
Detection of objects of a given class is important for many applications. However it is difficult
to learn a general detector with high detection rate as well as low false alarm rate …
to learn a general detector with high detection rate as well as low false alarm rate …
Robust discrete synthesis against unspecified disturbances
Systems working in uncertain environments should possess a robustness property, which
ensures that the behaviours of the system remain close to the original behaviours under the …
ensures that the behaviours of the system remain close to the original behaviours under the …
In-place decomposition for robustness in FPGA
JY Lee, Z Feng, L He - 2010 IEEE/ACM International …, 2010 - ieeexplore.ieee.org
The programmable logic block (PLB) in a modern FPGA features a built-in carry chain (or
adder) and a decomposable LUT, where such an LUT may be decomposed into two or more …
adder) and a decomposable LUT, where such an LUT may be decomposed into two or more …
LUT-based FPGA technology map** for reliability
As device size shrinks to the nanometer range, FPGAs are increasingly prone to
manufacturing defects. We anticipate that the ability to tolerate multiple defects will be very …
manufacturing defects. We anticipate that the ability to tolerate multiple defects will be very …
Reliability-oriented placement and routing algorithm for SRAM-based FPGAs
As the feature size shrinks to the nanometer scale, SRAM-based FPGAs will become
increasingly vulnerable to soft errors. Existing reliability-oriented placement and routing …
increasingly vulnerable to soft errors. Existing reliability-oriented placement and routing …
Fault-tolerant resynthesis with dual-output LUTs
We present a fault-tolerant post-map** resynthesis for FPGA-based designs that exploits
the dual-output feature of modern FPGA architectures to improve the reliability of a mapped …
the dual-output feature of modern FPGA architectures to improve the reliability of a mapped …
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms
N **g, JY Lee, Z Feng, W He, Z Mao, L He - ACM Transactions on …, 2013 - dl.acm.org
Reliability has become an increasingly important concern for SRAM-based field
programmable gate arrays (FPGAs). Targeting SEU (single event upset) in SRAM-based …
programmable gate arrays (FPGAs). Targeting SEU (single event upset) in SRAM-based …
AIP-SEM: An Efficient ML-Boost In-Place Soft Error Mitigation Method for SRAM-Based FPGA
Z Wang, L Chen, S Wang, J Zhou… - … of Electronics Design …, 2024 - ieeexplore.ieee.org
With the wide application of SRAM-base FPGA in aerospace engineering, the radiation
resistance performance of FPGAs becomes unprecedented important. To correct errors, the …
resistance performance of FPGAs becomes unprecedented important. To correct errors, the …
A theory of robust omega-regular software synthesis
A key property for systems subject to uncertainty in their operating environment is
robustness: ensuring that unmodeled but bounded disturbances have only a proportionally …
robustness: ensuring that unmodeled but bounded disturbances have only a proportionally …