The performance of high-speed wireline data links depend crucially on the quality and
precision of their clocking infrastructure. For future applications, such as microprocessor …

This paper describes Convex1, a convex optimization modeling framework in Julia. Convex
translates problems from a user-friendly functional language into an abstract syntax tree …

A digital delay-locked loop (DLL) that achieves infinite phase range and 40-ps worst case
phase resolution at 400 MHz was developed in a 3.3-V, 0.4-/spl mu/m standard CMOS …

A folded multitap transmitter equalizer and multitap receiver equalizer counteract the losses
and reflections present in the backplane environment. A flexible 2-PAM/4-PAM clock data …

This paper presents a 90-nm CMOS 10-Gb/s transceiver for chip-to-chip communications. To
mitigate the effects of channel loss and other impairments, a 5-tap decision feedback …

This paper describes an all-analog multiphase delay-locked loop (DLL) architecture that
achieves both wide-range operation and low-jitter performance. A replica delay line is …

We present a 4-Gb/s I/O circuit that fits in 0.1-mm/sup 2/of die area, dissipates 90 mW of
power, and operates over 1 m of 7-mil 0.5-oz PCB trace in a 0.25-/spl mu/m CMOS …

Emerging non-imaging ultrasound applications, such as ultrasonic wireless power delivery
to implantable devices and ultrasound neuromodulation, require wearable form factors …

A high-speed serial data transceiver includes multiple receivers and transmitters for
receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second …

Provides the only up-to-date source on the most recent advances in this often complex and
fascinating topic. The only book to be entirely devoted to clocking Clocking has become one …