An adaptive core map** algorithm on NoC for future heterogeneous system-on-chip
The map** analysis needs to have a complete performance assessment of Network-on-
Chip (NoC) based on delay, throughput, and energy consumption measurements. This …
Chip (NoC) based on delay, throughput, and energy consumption measurements. This …
A survey on fault-tolerant application map** techniques for network-on-chip
Reliability is becoming a major concern in Networks-on-Chips (NoCs) design. Several
techniques have been proposed in the literature to deal with different types of faults at …
techniques have been proposed in the literature to deal with different types of faults at …
Enhancing Reliability and Energy Efficiency in Many-Core Processors Through Fault-Tolerant Network-On-Chip
This article presents a proposal for fault-tolerant task map** on many-core processors to
enhance system performance and reduce communication energy. The proposed algorithm …
enhance system performance and reduce communication energy. The proposed algorithm …
Performance assessment of adaptive core map** for NoC-based architectures
In this trending technology of network-on-chip, the large number of cores embedded on-chip
had a rapid growth resulting in performance degradation. Many methodologies came into …
had a rapid growth resulting in performance degradation. Many methodologies came into …
Performance and communication energy constrained embedded benchmark for fault tolerant core map** onto NoC architectures
Due to the rapid growth of the components encapsulated on the on-chip architecture, the
performance degradation and communication issues between the cores significantly impact …
performance degradation and communication issues between the cores significantly impact …
Exact formulas for fault aware core map** on NoC reliability
One of the fundamentals of understanding a fault aware core map** for NoC reliability
needs the knowledge of the measure of failure probability and functional metrics. Below …
needs the knowledge of the measure of failure probability and functional metrics. Below …
System level fault-tolerance core map** and FPGA-based verification of NoC
NKR Becchu, VM Harishchandra… - Microelectronics …, 2017 - Elsevier
This paper proposes a fault-tolerance network on chip (FTNoC) algorithm that incorporates a
core graph unit, which is responsible for map** and scheduling the core graph on the …
core graph unit, which is responsible for map** and scheduling the core graph on the …
A gracefully degrading and energy-efficient fault tolerant NoC using spare core
Reliability is a significant strategy concern for modern day multi core embedded systems. On
chip communicating systems are vulnerable to permanent network faults and transient faults …
chip communicating systems are vulnerable to permanent network faults and transient faults …
High-performance and energy-efficient fault-tolerance core map** in NoC
NKR Beechu, VM Harishchandra… - … : Informatics and Systems, 2017 - Elsevier
Abstract Network on Chip (NoC) has been proposed as an efficient solution to
communication problems in on-chip processors. The probability of failure increases in these …
communication problems in on-chip processors. The probability of failure increases in these …
Hardware implementation of fault tolerance NoC core map**
NKR Beechu, V Moodabettu Harishchandra… - Telecommunication …, 2018 - Springer
Due to performance and reliability, network on chip (NoC) is considered to be the future
generation interconnect technique for multiple cores in a chip. This paper proposes a system …
generation interconnect technique for multiple cores in a chip. This paper proposes a system …