A survey of neuromorphic computing and neural networks in hardware
Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices,
and models that contrast the pervasive von Neumann computer architecture. This …
and models that contrast the pervasive von Neumann computer architecture. This …
Hybrid robust iris recognition approach using iris image pre‐processing, two‐dimensional gabor features and multi‐layer perceptron neural network/PSO
Computational intelligence is employed to solve factual and complicated global problems,
though neural networks (NNs) and evolutionary computing have also affected these issues …
though neural networks (NNs) and evolutionary computing have also affected these issues …
An efficient fpga-based convolutional neural network for classification: Ad-mobilenet
Convolutional Neural Networks (CNN) continue to dominate research in the area of
hardware acceleration using Field Programmable Gate Arrays (FPGA), proving its …
hardware acceleration using Field Programmable Gate Arrays (FPGA), proving its …
A novel systolic parallel hardware architecture for the FPGA acceleration of feedforward neural networks
New chips for machine learning applications appear, they are tuned for a specific topology,
being efficient by using highly parallel designs at the cost of high power or large complex …
being efficient by using highly parallel designs at the cost of high power or large complex …
Scalable serial hardware architecture of multilayer perceptron neural network for automatic wheezing detection
A Semmad, M Bahoura - Microprocessors and Microsystems, 2023 - Elsevier
This paper proposes a serial hardware architecture of a multilayer perceptron (MLP) neural
network for real-time wheezing detection in respiratory sounds. As an established …
network for real-time wheezing detection in respiratory sounds. As an established …
Deep neural network accelerator based on FPGA
TV Huynh - 2017 4th NAFOSTED Conference on Information …, 2017 - ieeexplore.ieee.org
In this work, we propose an efficient architecture for the hardware realization of deep neural
networks on reconfigurable computing platforms like FPGA. The proposed neural network …
networks on reconfigurable computing platforms like FPGA. The proposed neural network …
Improvement and implementation of wireless network topology system based on SNMP protocol for router equipment
H Wang - Computer Communications, 2020 - Elsevier
With the continuous expansion of computer network scale and the diversity of network
equipment, the traditional single computer network maintenance and management method …
equipment, the traditional single computer network maintenance and management method …
Hardware implementation of tanh exponential activation function using fpga
S Bouguezzi, H Faiedh, C Souani - 2021 18th International …, 2021 - ieeexplore.ieee.org
The most active research area for Field Programmable Gate Arrays is the Convolution
Neural Network (CNN), and the gist of any CNN is an activation function. Therefore, various …
Neural Network (CNN), and the gist of any CNN is an activation function. Therefore, various …
Design and implementation for a high-efficiency hardware accelerator to realize the learning machine for predicting OLED degradation
IF Chang, HR Chen, PCP Chao - Microsystem Technologies, 2023 - Springer
A new learning machine based on neural network (NN) and its hardware accelerator are
successfully built in this study for predicting the luminance decay of Organic Light Emitting …
successfully built in this study for predicting the luminance decay of Organic Light Emitting …
A massively parallel pipelined reconfigurable design for M-PLN based neural networks for efficient image classification
Abstract Weightless Neural Networks (WNNs) are a powerful mechanism for pattern
recognition. Aiming at enhancing their learning capabilities, Multi-valued Probabilistic Logic …
recognition. Aiming at enhancing their learning capabilities, Multi-valued Probabilistic Logic …