[HTML][HTML] Field programmable gate array applications—A scientometric review

J Ruiz-Rosero, G Ramirez-Gonzalez, R Khanna - Computation, 2019 - mdpi.com
Field Programmable Gate Array (FPGA) is a general purpose programmable logic device
that can be configured by a customer after manufacturing to perform from a simple logic gate …

A PUF-enabled secure architecture for FPGA-based IoT applications

AP Johnson, RS Chakraborty… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
The Internet of Things (IoT) is a dynamic, ever-evolving “living” entity. Hence, modern Field
Programmable Gate Array (FPGA) devices with Dynamic Partial Reconfiguration (DPR) …

Towards rapid dynamic partial reconfiguration in video-based driver assistance systems

C Claus, R Ahmed, F Altenried, W Stechele - … : Architectures, Tools and …, 2010 - Springer
Using dynamically reconfigurable hardware is useful especially when a high degree of
flexibility is demanded and the application requires inherent parallelism to achieve real-time …

FaRM: Fast reconfiguration manager for reducing reconfiguration time overhead on FPGA

F Duhem, F Muller, P Lorenzini - International Symposium on Applied …, 2011 - Springer
In this paper, we present a fast ICAP controller providing high-speed configuration and easy-
to-use readback capabilities, reducing configuration overhead as much as possible. In order …

Fault attack on AES via hardware Trojan insertion by dynamic partial reconfiguration of FPGA over ethernet

AP Johnson, S Saha, RS Chakraborty… - Proceedings of the 9th …, 2014 - dl.acm.org
We describe a novel methodology to exploit the widely used Dynamic Partial
Reconfiguration (DPR) support in Field Programmable Gate Arrays (FPGAs) to implant a …

[HTML][HTML] A run-time reconfiguration method for an FPGA-based electrical capacitance tomography system

D Wanta, WT Smolik, J Kryszyn, P Wróblewski… - Electronics, 2022 - mdpi.com
A desirable feature of an electrical capacitance tomography system is the adaptation
possibility to any sensor configuration and measurement mode. A run-time reconfiguration of …

Reconfiguration time overhead on field programmable gate arrays: reduction and cost model

F Duhem, F Muller, P Lorenzini - IET Computers & Digital Techniques, 2012 - IET
Partial reconfiguration suffers from low performance and thus its use is limited when the
reconfiguration overhead is too high compared to the task execution time. To overcome this …

A High‐Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active …

JC Hoffman, MS Pattichis - International journal of …, 2011 - Wiley Online Library
Dynamically reconfigurable computing platforms provide promising methods for dynamic
management of hardware resources, power, and performance. Yet, progress in dynamically …

UML design for dynamically reconfigurable multiprocessor embedded systems

J Vidal, F De Lamotte, G Gogniat… - … , Automation & Test …, 2010 - ieeexplore.ieee.org
In this paper we propose a design methodology to explore partial and dynamic
reconfiguration of modern FPGAs. We improve an UML based co-design methodology to …

System-level security for network processors with hardware monitors

K Hu, T Wolf, T Teixeira, R Tessier - Proceedings of the 51st Annual …, 2014 - dl.acm.org
New attacks are emerging that target the Internet infrastructure. Modern routers use
programmable network processors that may be exploited by merely sending suitably crafted …