Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines
M Abdallah - US Patent 9,842,005, 2017 - Google Patents
A system for executing instructions using a plurality of register file segments for a processor.
The system includes a global front end scheduler for receiving an incoming instruction …
The system includes a global front end scheduler for receiving an incoming instruction …
Method for dependency broadcasting through a source organized source view data structure
M Abdallah - US Patent 10,275,255, 2019 - Google Patents
(57) ABSTRACT A method for dependency broadcasting through a source organized source
view data structure. The method includes receiving an incoming instruction sequence using …
view data structure. The method includes receiving an incoming instruction sequence using …
Method for dependency broadcasting through a block organized source view data structure
M Abdallah - US Patent 9,934,042, 2018 - Google Patents
A method for dependency broadcasting through a block organized source view data
structure. The method includes receiving an incoming instruction sequence using a global …
structure. The method includes receiving an incoming instruction sequence using a global …
Transforming non-contiguous instruction specifiers to contiguous instruction specifiers
MK Gschwind - US Patent 9,280,347, 2016 - Google Patents
6,009.261 6,094,695 6,185,629 6,189,088 6, 192466 6,308,255 6,334, 176 6,338,057
6,349,361 6,381,691 6,408,383 6,449,706 6.463, 582 6,499,116 6,513,109 6,570,511 …
6,349,361 6,381,691 6,408,383 6,449,706 6.463, 582 6,499,116 6,513,109 6,570,511 …
Vector string range compare
JD Bradury, EM Schwarz, TJ Slegel - US Patent 9,442,722, 2016 - Google Patents
Processing of character data is facilitated. A Vector String Range Compare instruction is
provided that compares each element of a vector with a range of values based on a set of …
provided that compares each element of a vector with a range of values based on a set of …
Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
M Abdallah - US Patent 9,766,893, 2017 - Google Patents
A method for executing instructions using a plurality of virtual cores for a processor. The
method includes receiving an incoming instruction sequence using a global front end …
method includes receiving an incoming instruction sequence using a global front end …
Methods, systems and apparatus for predicting the way of a set associative cache
M Abdallah, R Rao, K Avudaiyappan - US Patent 9,904,625, 2018 - Google Patents
A method for predicting a way of a set associative shadow cache is disclosed. As a part of a
method, a request to fetch a first far taken branch instruction of a first cache line from an …
method, a request to fetch a first far taken branch instruction of a first cache line from an …
Method for performing dual dispatch of blocks and half blocks
M Abdallah - US Patent 9,811,342, 2017 - Google Patents
A method for executing dual dispatch of blocks and half blocks. The method includes
receiving an incoming instruction sequence using a global front end; grou** the …
receiving an incoming instruction sequence using a global front end; grou** the …
Method for implementing a reduced size register view data structure in a microprocessor
MA Abdallah - US Patent 9,891,924, 2018 - Google Patents
A method for implementing a reduced size register view data structure in a microprocessor.
The method includes receiving an incoming instruction sequence using a global front end; …
The method includes receiving an incoming instruction sequence using a global front end; …
Method for executing multithreaded instructions grouped into blocks
M Abdallah - US Patent 9,811,377, 2017 - Google Patents
(57) ABSTRACT A method for executing multithreaded instructions grouped into blocks. The
method includes receiving an incoming instruction sequence using a global front end; …
method includes receiving an incoming instruction sequence using a global front end; …