[BOOK][B] The Electrical Engineering Handbook-Six Volume Set
RC Dorf - 2018 - api.taylorfrancis.com
In two editions spanning more than a decade, The Electrical Engineering Handbook stands
as the definitive reference to the multidisciplinary field of electrical engineering. Our …
as the definitive reference to the multidisciplinary field of electrical engineering. Our …
A compact and high-performance hardware architecture for CRYSTALS-Dilithium
The lattice-based CRYSTALS-Dilithium scheme is one of the three thirdround digital
signature finalists in the National Institute of Standards and Technology Post-Quantum …
signature finalists in the National Institute of Standards and Technology Post-Quantum …
VLSI architectures for discrete wavelet transforms
KK Parhi, T Nishitani - IEEE Transactions on Very Large Scale …, 1993 - ieeexplore.ieee.org
A folded architecture and a digit-serial architecture are proposed for implementation of one-
and two-dimensional discrete wavelet transforms. In the one-dimensional folded …
and two-dimensional discrete wavelet transforms. In the one-dimensional folded …
Pipelined parallel FFT architectures via folding transformation
This paper presents a novel approach to develop parallel pipelined architectures for the fast
Fourier transform (FFT). A formal procedure for designing FFT architectures using folding …
Fourier transform (FFT). A formal procedure for designing FFT architectures using folding …
Low-energy digit-serial/parallel finite field multipliers
L Song, KK Parhi - Journal of VLSI signal processing systems for signal …, 1998 - Springer
Digit-serial architectures are best suited for systems requiring moderate sample rate and
where area and power consumption are critical. This paper presents a new approach for …
where area and power consumption are critical. This paper presents a new approach for …
Low-latency sequential and overlapped architectures for successive cancellation polar decoder
C Zhang, KK Parhi - IEEE Transactions on Signal Processing, 2013 - ieeexplore.ieee.org
Polar codes have recently emerged as one of the most favorable capacityachieving error
correction codes due to their low encoding and decoding complexity. However, because of …
correction codes due to their low encoding and decoding complexity. However, because of …
A programmable hyper-dimensional processor architecture for human-centric IoT
Hyper-dimensional Computing (HDC), a bio-inspired paradigm defined on random high-
dimensional vectors, has emerged as a promising IoT paradigm. It is known to provide …
dimensional vectors, has emerged as a promising IoT paradigm. It is known to provide …
Obfuscating DSP circuits via high-level transformations
This paper presents a novel approach to design obfuscated circuits for digital signal
processing (DSP) applications using high-level transformations, a key-based obfuscating …
processing (DSP) applications using high-level transformations, a key-based obfuscating …
High-level algorithm and architecture transformations for DSP synthesis
KK Parhi - Journal of VLSI signal processing systems for signal …, 1995 - Springer
This survey paper reviews numerous high-level transformation techniques which can be
applied at the algorithm or the architecture level to improve the performance of digital signal …
applied at the algorithm or the architecture level to improve the performance of digital signal …
PaReNTT: Low-latency parallel residue number system and NTT-based long polynomial modular multiplication for homomorphic encryption
High-speed long polynomial multiplication is important for applications in homomorphic
encryption (HE) and lattice-based cryptosystems. This paper addresses low-latency …
encryption (HE) and lattice-based cryptosystems. This paper addresses low-latency …