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A survey on low-power techniques with emerging technologies: From devices to systems
Nowadays, power consumption is one of the main limitations of electronic systems. In this
context, novel and emerging devices provide new opportunities to extend the trend toward …
context, novel and emerging devices provide new opportunities to extend the trend toward …
A 0.4-V 0.66-fJ/cycle retentive true-single-phase-clock 18T flip-flop in 28-nm fully-depleted SOI CMOS
In this paper, we propose an 18-transistor true-single-phase-clock (TSPC) flip-flop (FF) with
static data retention based on two forward-conditional feedback loops, without increasing …
static data retention based on two forward-conditional feedback loops, without increasing …
UTBB FDSOI technology flexibility for ultra low power internet-of-things applications
E Beigné, JF Christmann, A Valentian… - 2015 45th European …, 2015 - ieeexplore.ieee.org
In this paper, we propose to analyze FDSOI technology suitability for IoT applications and
more specifically for autonomous Wireless Sensor Nodes. As IoT applications are extremely …
more specifically for autonomous Wireless Sensor Nodes. As IoT applications are extremely …
All-digital embedded meters for on-line power estimation
Modern low power designs use multiple knobs for concurrent dynamic and leakage power
optimization; supply voltage and threshold voltage are the most adopted. An efficient control …
optimization; supply voltage and threshold voltage are the most adopted. An efficient control …
Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology
B Pelloux-Prayer, A Valentian, B Giraud… - 2013 IFIP/IEEE 21st …, 2013 - ieeexplore.ieee.org
Ultra-Thin Body and BOX Fully-Depleted SOI (UTBB FD-SOI) technology is one of two
candidate technologies for replacing Bulk technology at sub-20nm nodes. Although it …
candidate technologies for replacing Bulk technology at sub-20nm nodes. Although it …
Performance analysis of multi-VT design solutions in 28nm UTBB FD-SOI technology
B Pelloux-Prayer, M Blagojević… - 2013 IEEE SOI-3D …, 2013 - ieeexplore.ieee.org
UTBB FD-SOI technology is able to reach very high speeds thanks to flip-Wells variant which
enables low-V T (LVT) tuning. This approach appears to be the best design option to catch …
enables low-V T (LVT) tuning. This approach appears to be the best design option to catch …
Analysis of advanced circuits for SET measurement
Single Event Transients (SETs) are a growing concern in advanced integrated circuits yet
techniques to accurately characterize the cross-section and pulse width of SETs are less …
techniques to accurately characterize the cross-section and pulse width of SETs are less …
Non-volatility for ultra-low power asynchronous circuits in hybrid cmos/magnetic technology
E Zianbetov, E Beigné… - 2015 21st IEEE …, 2015 - ieeexplore.ieee.org
This paper addresses the power reduction techniques for the ultra-low power integrated
circuits. We propose to implement non-volatile asynchronous circuits which will have a quasi …
circuits. We propose to implement non-volatile asynchronous circuits which will have a quasi …
A 0.4 V 0.08 fJ/cycle retentive true-single-phase-clock 18T flip-flop in 28nm FDSOI CMOS
In this paper, we propose an 18-transistor (18T) True-Single-Phase-Clock (TSPC) Flip-Flop
(FF) with static data retention based on two forward-conditional feedback loops, without …
(FF) with static data retention based on two forward-conditional feedback loops, without …
Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect
In this paper, we analyze the electrical behavior of logic gates in presence of defect for
different technologies. The final objective is to compare the defect detectability in a …
different technologies. The final objective is to compare the defect detectability in a …