Recent progress on negative capacitance tunnel FET for low-power applications: Device perspective

AK Upadhyay, SB Rahi, S Tayal, YS Song - Microelectronics Journal, 2022 - Elsevier
In the present-day scenario of low-power electronics, there is a steady and increasing need
for an adequate device that can counteract the power dissipation issue due to the consistent …

Pentagonal 2D Transition Metal Dichalcogenides: PdSe2 and Beyond

Q Liang, Z Chen, Q Zhang… - Advanced Functional …, 2022 - Wiley Online Library
Abstract 2D materials with common hexagonal crystal structures, such as graphene,
hexagonal boron nitride, and transition metal dichalcogenides have attracted great interest …

Negative capacitance field effect transistors based on van der Waals 2D materials

RS Chen, Y Lu - Small, 2024 - Wiley Online Library
Steep subthreshold swing (SS) is a decisive index for low energy consumption devices.
However, the SS of conventional field effect transistors (FETs) has suffered from Boltzmann …

Steep-subthreshold slope dual gate negative capacitance junction less FET with dead channel: TCAD approach for digital/RF applications

S Chaudhary, B Dewan, C Sahu, M Yadav - Microelectronics Journal, 2022 - Elsevier
In pursuit of lowering power densities and reducing energy efficiency constraints, execution
grid of arising electronic devices are being investigated to track down alternative options for …

Analytical model of subthreshold drain current for nanoscale negative capacitance junctionless FinFET

S Kaushal, AK Rana - Microelectronics Journal, 2022 - Elsevier
In this article, an analytical Subthreshold Drain Current model has been developed for
Negative Capacitance Junctionless FinFET (NC-JL FinFET). To obtain the subthreshold …

Nonhysteretic condition in negative capacitance junctionless FETs

A Rassekh, F Jazaeri, JM Sallese - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
This article analyzes the design space stability of negative capacitance double-gate
junctionless field-effect transistors (NCDG JLFETs). Using analytical expressions derived …

Investigation of 4H-SiC gate-all-around cylindrical nanowire junctionless MOSFET including negative capacitance and quantum confinements

D Madadi, AA Orouji - The European Physical Journal Plus, 2021 - Springer
In our work, we demonstrate a 4H-SiC gate-all-around cylindrical nanowire junctionless
(GAA-NWJL) metal oxide field effect transistor (MOSFET) with a negative capacitance (NC) …

Design space of negative capacitance in FETs

A Rassekh, F Jazaeri, JM Sallese - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
Relying on the previously developed charge-based approaches, this paper presents a
physics-based design space of negative capacitance in double-gate and bulk MOSFET …

Unconventional VTC of subthreshold inverter with MFMIS negative capacitance transistor: An analytical modelling framework with implications for ultralow power logic …

S Semwal, A Kranti - Semiconductor Science and Technology, 2022 - iopscience.iop.org
The present reports an analytical modelling framework to provide insights into subthreshold
logic design using metal-ferroelectric-metal–insulator-semiconductor (MFMIS) negative …

Performance evaluation of gate engineered ferroelectric MIMOS for analog/electrical IC applications

Y Pathak, K Verma, BD Malhotra, R Chaujar - Physica Scripta, 2024 - iopscience.iop.org
This work examines various materials for gate electrode for enhancing the performance of M-
Fe-MIMOS (Metal Ferroelectric Metal Insulator Metal Oxide Semiconductor Field Effect …