Nested transactional memory (TM) facilitates software composition by letting one module
invoke another without either knowing whether the other uses transactions. Closed nested …

Split hardware transaction techniques may support execution of serial and parallel nesting
of code within an atomic block to an arbitrary nesting depth. An atomic block including child …

Due to power wall, memory wall, and ILP wall, we are facing the end of ever increasing
single-threaded performance. For this reason, multicore and manycore processors are …

An apparatus, method, and system for implementing a hardware transactional memory
(HTM) system with multiple levels of transactional buffers. The apparatus comprises a data …

Exploiting the emerging reality of affordable multi-core architectures goes through providing
programmers with simple abstractions that would enable them to easily turn their sequential …

a transactional memory interface allows a programmer to designate certain sequences of
operations as “atomic blocks”, which are guaranteed by the transactional memory …

Multi-core chips are now commonplace in server, desktop, and even embedded systems;
however, these chips create an inflection point for mainstream software development. To …

In this paper, we evaluate the emerging Transactional Memory (TM) area by develo** a
set of Java transactional memory workloads and studying their performance under a Java …

Transactional Memory (TM) shows promise as a new concurrency control mechanism to
replace lock-based synchronization. However, there have been few studies of TM systems …

Program traces—multiple basic blocks that frequently execute in succession as a group—
are a useful unit for code manipulation and optimization, especially in dynamic binary …