The Nesterov's method approach to analytic placement has recently demonstrated strong
solution quality and scalability. We dissect the previous implementation strategy and show …

Placement is essential in very large-scale integration (VLSI) physical design, as it directly
affects the design cycle. Despite extensive prior research on placement, achieving fast and …

In this paper, we present an optimization flow for monolithic 3D ICs called Pin-3D Optimizer.
Compared with the state-of-the-art RTL-to-GDS flows that rely on ad-hoc technology file …

Despite the recent academic efforts to develop Electronic Design Automation (EDA)
algorithms for 3D ICs, the current market does not have commercial 3D computer-aided …

3D integration technology is one of the leading options that can advance Moore's Law
beyond conventional scaling. Due to the absence of commercial 3D placers and routers …

This paper proposes a high-quality 3D placement algorithm to determine the positions of
standard cells and inter-die vias to optimize wirelength considering multiple manufacturing …

State-of-the-art 3D IC Place-and-Route flows were designed with older technology nodes
and aggressive bonding pitch assumptions. As a result, these flows fail to honor the width …

In this article, we present a new analytical 3-D placement framework with a bistratal
wirelength model for faceto-face-bonded 3-D ICs with heterogeneous technology nodes …

High-density 3D techniques (such as wafer bonding and monolithic-3D) show tremendous
promise in reducing interconnect lengths and relieving 2D congestion. We propose an …

This paper proposes a mixed-size 3D analytical placement framework for face-to-face
stacked integrated circuits fabricated with heterogeneous technology nodes and connected …