Map** techniques in multicore processors: current and future trends
Multicore systems are in demand due to their high performance thus making application
map** an important research area in this field. Breaking an application into multiple …
map** an important research area in this field. Breaking an application into multiple …
Online task remap** strategies for fault-tolerant network-on-chip multiprocessors
O Derin, D Kabakci, L Fiorin - Proceedings of the Fifth ACM/IEEE …, 2011 - dl.acm.org
As CMOS technology scales down into the deep-submicron domain, the aspects of fault
tolerance in complex Networks-on-Chip (NoCs) architectures are assuming an increasing …
tolerance in complex Networks-on-Chip (NoCs) architectures are assuming an increasing …
Minimizing cost of scheduling tasks on heterogeneous multicore embedded systems
Cost savings are very critical in modern heterogeneous computing systems, especially in
embedded systems. Task scheduling plays an important role in cost savings. In this article …
embedded systems. Task scheduling plays an important role in cost savings. In this article …
Energy optimization for data allocation with hybrid SRAM+ NVM SPM
The gradually widening disparity in the speed of the CPU and memory has become a
bottleneck for the development of chip multiprocessor (CMP) systems. Increasing penalties …
bottleneck for the development of chip multiprocessor (CMP) systems. Increasing penalties …
Multi-objective map** optimization via problem decomposition for many-core systems
Due to the trend of many-core systems for dynamic multimedia applications, the problem
size of map** optimization gets bigger than ever making conventional meta-heuristics no …
size of map** optimization gets bigger than ever making conventional meta-heuristics no …
Decentralized dynamic resource management support for massively parallel processor arrays
This paper presents a hardware-supported resource management methodology for
massively parallel processor arrays. It enables processing elements to autonomously …
massively parallel processor arrays. It enables processing elements to autonomously …
Model-based parallelizer for embedded control systems on single-isa heterogeneous multicore processors
Z Zhong, M Edahiro - 2018 International SoC Design …, 2018 - ieeexplore.ieee.org
This paper presents a model-based parallelization approach for embedded systems on
single instruction set architecture (ISA) heterogeneous multicore processors, wherein the …
single instruction set architecture (ISA) heterogeneous multicore processors, wherein the …
An ILP approach for map** autosar runnables on multi-core architectures
AUTOSAR (AUTomotive Open System ARchitecture) standard was developed in order to
manage the complexity of automotive E/E (Electrical/Electronic) architectures. It provides a …
manage the complexity of automotive E/E (Electrical/Electronic) architectures. It provides a …
An optimized map** algorithm based on simulated annealing for regular NoC architecture
Network on chip (NoC) architecture is viewed as a potential solution for the interconnect
demands of the emerging multi-core systems since it renders the system high performance …
demands of the emerging multi-core systems since it renders the system high performance …
Multi-criteria optimization for map** programs to multi-processors
Finding tradeoffs in design space is naturally formulated as a multicriteria optimization
problem. In this paper, we model tradeoffs between communication cost and the balance of …
problem. In this paper, we model tradeoffs between communication cost and the balance of …