Advancing sdn from openflow to p4: A survey

A Liatifis, P Sarigiannidis, V Argyriou… - ACM Computing …, 2023 - dl.acm.org
Software-defined Networking (SDN) marked the beginning of a new era in the field of
networking by decoupling the control and forwarding processes through the OpenFlow …

A survey on data plane programming with p4: Fundamentals, advances, and applied research

F Hauser, M Häberle, D Merling, S Lindner… - Journal of Network and …, 2023 - Elsevier
Programmable data planes allow users to define their own data plane algorithms for network
devices including appropriate data plane application programming interfaces (APIs) which …

Pushing the level of abstraction of digital system design: A survey on how to program fpgas

ED Sozzo, D Conficconi, A Zeni, M Salaris… - ACM Computing …, 2022 - dl.acm.org
Field Programmable Gate Arrays (FPGAs) are spatial architectures with a heterogeneous
reconfigurable fabric. They are state-of-the-art for prototy**, telecommunications …

Waverunner: An elegant approach to hardware acceleration of state machine replication

M Alimadadi, H Mai, S Cho, M Ferdman… - … USENIX Symposium on …, 2023 - usenix.org
State machine replication (SMR) is a core mechanism for building highly available and
consistent systems. In this paper, we propose Waverunner, a new approach to accelerate …

A survey on FPGA support for the feasible execution of virtualized network functions

GS Niemiec, LMS Batista… - … Surveys & Tutorials, 2019 - ieeexplore.ieee.org
Network Functions Virtualization (NFV) has received considerable attention in the past few
years, both from industry and academia, due to its potential for reducing capital and …

[HTML][HTML] The design of a dynamic configurable packet parser based on fpga

Y Sun, Z Guo - Micromachines, 2023 - mdpi.com
To meet the evolving demands of programmable networks and address the limitations of
traditional fixed-type protocol parsers, we propose a dynamic and configurable low-latency …

A custom processor for protocol-independent packet parsing

H Zolfaghari, D Rossi, J Nurmi - Microprocessors and Microsystems, 2020 - Elsevier
Networking devices such as switches and routers have traditionally had fixed functionality.
They have the logic for the union of network protocols matching the application and market …

Multi buses: Theory and practical considerations of data bus width scaling in FPGAs

L Kekely, J Cabal, V Puš… - 2020 23rd Euromicro …, 2020 - ieeexplore.ieee.org
As the throughput of computer networks and other peripheral interfaces is rising, developers
are forced to use ever-wider data buses in FPGA designs. However, utilization of wide buses …

Multi-Table Programmable Parser with online flow-level update consistency for satellite networks

J Zhang, D Wang, K Liu, J Lu - Computer Networks, 2024 - Elsevier
Programmable packet parsers in the space data plane, responsible for identifying protocols
and extracting keywords on demand, are significant to realize protocol upgrading for satellite …

The design of a configurable and low-latency packet parsing system for communication networks

KS Hsu, CA Shen - Telecommunication Systems, 2023 - Springer
Parsing is a critical packet processing function in the network node, and the performance
and configurability of the packet parsing is essential for designing a low-latency and highly …