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Attack directories, not caches: Side channel attacks in a non-inclusive world
M Yan, R Sprabery, B Gopireddy… - … IEEE Symposium on …, 2019 - ieeexplore.ieee.org
Although clouds have strong virtual memory isolation guarantees, cache attacks stemming
from shared caches have proved to be a large security problem. However, despite the past …
from shared caches have proved to be a large security problem. However, despite the past …
Ric: Relaxed inclusion caches for mitigating llc side-channel attacks
Recently, side-channel attacks on Last Level Caches (LLCs) were demonstrated. The
attacks require the ability to evict critical data from the cache hierarchy, making future …
attacks require the ability to evict critical data from the cache hierarchy, making future …
The University of Chicago
ES - Minerva, 1975 - JSTOR
On 20 March, 1974, Professor Edward Banfield, of the University of Pennsylvania, was
prevented from delivering a lecture at the University of Chicago. Professor Banfield, who is a …
prevented from delivering a lecture at the University of Chicago. Professor Banfield, who is a …
Secdir: a secure directory to defeat directory side-channel attacks
Directories for cache coherence have been recently shown to be vulnerable to conflict-
based side-channel attacks. By forcing directory conflicts, an attacker can evict victim …
based side-channel attacks. By forcing directory conflicts, an attacker can evict victim …
Understanding I/O direct cache access performance for end host networking
Direct Cache Access (DCA) enables a network interface card (NIC) to load and store data
directly on the processor cache, as conventional Direct Memory Access (DMA) is no longer …
directly on the processor cache, as conventional Direct Memory Access (DMA) is no longer …
Advances in microprocessor cache architectures over the last 25 years
Over the last 25 years, the use of caches has advanced significantly in mainstream
microprocessors to address the memory wall challenge. As we transformed microprocessors …
microprocessors to address the memory wall challenge. As we transformed microprocessors …
The reuse cache: Downsizing the shared last-level cache
Over recent years, a growing body of research has shown that a considerable portion of the
shared last-level cache (SLLC) is dead, meaning that the corresponding cache lines are …
shared last-level cache (SLLC) is dead, meaning that the corresponding cache lines are …
Double trouble: Combined heterogeneous attacks on {Non-Inclusive} cache hierarchies
As the performance of general-purpose processors faces diminishing improvements,
computing systems are increasingly equipped with domain-specific accelerators. Today's …
computing systems are increasingly equipped with domain-specific accelerators. Today's …
Time is money, friend! timing side-channel attack against garbled circuit constructions
With the advent of secure function evaluation (SFE), distrustful parties can jointly compute on
their private inputs without disclosing anything besides the results. Yao's garbled circuit …
their private inputs without disclosing anything besides the results. Yao's garbled circuit …
Hemiola: A DSL and verification tools to guide design and proof of hierarchical cache-coherence protocols
Cache-coherence protocols have been one of the greatest challenges in formal verification
of hardware, due to their central complication of executing multiple memory-access …
of hardware, due to their central complication of executing multiple memory-access …