Stencil computation sweeps over a spatial grid over multiple time steps to perform nearest-
neighbor computations. The bandwidth-to-compute requirement for a large class of stencil …

Most stencil computations allow tile-wise concurrent start, ie, there always exists a face of
the iteration space and a set of tiling hyperplanes such that all tiles along that face can be …

Stencil computations are widely used from physical simulations to machine-learning. They
are embarrassingly parallel and perfectly fit modern hardware such as Graphic Processing …

Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known
technique to localize their computation. When ISLs are tiled across a parallel architecture …

Several parallel architectures such as GPUs and the Cell processor have fast explicitly
managed on-chip memories, in addition to slow off-chip memory. They also have very high …

We present a time skewing algorithm that breaks the memory wall for certain iterative stencil
computations. A stencil computation, even with constant weights, is a completely memory …

Tiling is a widely used loop transformation for exposing/exploiting parallelism and data
locality. High-performance implementations use multiple levels of tiling to exploit the …

Many scientific applications operate in a bulk-synchronous mode of iterative communication
and computation steps. Even though the communication steps happen at the same logical …

In high-performance systems, stencil computations play a crucial role as they appear in a
variety of different fields of application, ranging from partial differential equation solving, to …

Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known
technique to localize their computation. When ISLs are tiled across a parallel architecture …