Reconfigurable turbo decoder with parallel architecture for 3GPP LTE system

CC Wong, HC Chang - … Transactions on Circuits and Systems II …, 2010‏ - ieeexplore.ieee.org
This brief presents a parallel architecture for the turbo decoder using the quadratic
permutation polynomial interleaver. The supported block size ranges from 40 to 6144 with …

Area-efficient scalable MAP processor design for high-throughput multistandard convolutional turbo decoding

CH Lin, CY Chen, AY Wu - IEEE Transactions on Very Large …, 2009‏ - ieeexplore.ieee.org
Most of advanced wireless standards, such as WiMAX and LTE, have adopted different
convolutional turbo code (CTC) schemes with various block sizes and throughput rates …

An empirical analysis of concatenated polar codes for 5G wireless communication

N Radha, M Maheswari - Telecommunication Systems, 2024‏ - Springer
This paper aims to explore the potential benefits and performance enhancements of
combining a novel error correction code with polar codes through serial and parallel …

Reverse calculation-based low memory turbo decoder for power constrained applications

M Zhan, Z Pang, K Yu, H Wen - IEEE Transactions on Circuits …, 2021‏ - ieeexplore.ieee.org
Turbo codes are a family of near Shannon limit error correction coding schemes that usually
are adopted for wireless data transmission. To reduce the power dissipation of a long-term …

Implementation trade-offs of soft-input soft-output MAP decoders for convolutional codes

C Studer, S Fateh, C Benkeser… - IEEE Transactions on …, 2012‏ - ieeexplore.ieee.org
Soft-input soft-output (SISO) maximum a-posteriori (MAP) decoders for convolutional codes
(CCs) are an integral part of many modern wireless communication systems. Specifically …

Turbo NOC: A framework for the design of network-on-chip-based turbo decoder architectures

M Martina, G Masera - … Transactions on Circuits and Systems I …, 2010‏ - ieeexplore.ieee.org
This paper proposes a general framework for the design and simulation of network-on-chip-
based turbo decoder architectures. Several parameters in the design space are …

High-efficiency processing schedule for parallel turbo decoders using QPP interleaver

CC Wong, HC Chang - … Transactions on Circuits and Systems I …, 2011‏ - ieeexplore.ieee.org
This paper presents a high-efficiency parallel architecture for a turbo decoder using a
quadratic permutation polynomial (QPP) interleaver. Conventionally, two half-iterations for …

[HTML][HTML] Performance comparisons of broadband power line communication technologies

YM Chung - Applied Sciences, 2020‏ - mdpi.com
Broadband power line communication (PLC) is used as a communication technique for
advanced metering infrastructure (AMI) in Korea. High-speed (HS) PLC specified in …

Reconfigurable parallel turbo decoder design for multiple high-mobility 4G systems

CH Lin, CY Chen, EJ Chang, AY Wu - Journal of Signal Processing …, 2013‏ - Springer
For high-mobility 4G applications of LTE-A and WiMAX-2 systems, this paper presents a
dual-standard turbo decoder design with the following three techniques. 1) Circular parallel …

Reverse rate matching for low-power LTE-advanced turbo decoders

I Yoo, B Kim, IC Park - … Transactions on Circuits and Systems I …, 2015‏ - ieeexplore.ieee.org
In this paper, a reverse rate matching method is presented for LTE-Advanced turbo
decoders. In LTE-Advanced systems, the turbo codes are highly punctured to achieve high …