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Enhancing Reliability and Energy Efficiency in Many-Core Processors Through Fault-Tolerant Network-On-Chip
BNK Reddy, MZU Rahman… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
This article presents a proposal for fault-tolerant task map** on many-core processors to
enhance system performance and reduce communication energy. The proposed algorithm …
enhance system performance and reduce communication energy. The proposed algorithm …
Achieving super-linear speedup across multi-fpga for real-time dnn inference
Real-time Deep Neural Network (DNN) inference with low-latency requirement has become
increasingly important for numerous applications in both cloud computing (eg, Apple's Siri) …
increasingly important for numerous applications in both cloud computing (eg, Apple's Siri) …
Heterogeneous fpga-based cost-optimal design for timing-constrained cnns
Field programmable gate array (FPGA) has been one of the most popular platforms to
implement convolutional neural networks (CNNs) due to its high performance and cost …
implement convolutional neural networks (CNNs) due to its high performance and cost …
Thermal and performance efficient on-chip surface-wave communication for many-core systems in dark silicon era
Due to the exceedingly high integration density of VLSI circuits and the resulting high power
density, thermal integrity became a major challenge. One way to tackle this problem is Dark …
density, thermal integrity became a major challenge. One way to tackle this problem is Dark …
Thermal-aware task map** on dynamically reconfigurable network-on-chip based multiprocessor system-on-chip
Dark silicon is the phenomenon that a fraction of many-core chip has to be turned off or run
in a low-power state in order to maintain the safe chip temperature. System-level thermal …
in a low-power state in order to maintain the safe chip temperature. System-level thermal …
Energy-efficient and high-performance NoC architecture and map** solution for deep neural networks
With the advancement and miniaturization of transistor technology, hundreds of cores can
be integrated on a single chip. Network-on-Chips (NoCs) are the de facto on-chip …
be integrated on a single chip. Network-on-Chips (NoCs) are the de facto on-chip …
Fault-tolerant application map** on mesh-of-tree based network-on-chip
Abstract Network-on-Chip (NoC) has been considered as an efficient communication
infrastructure to support Multi-Processor System-on-Chip (MPSoC) design requirements for …
infrastructure to support Multi-Processor System-on-Chip (MPSoC) design requirements for …
BiGNoC: Accelerating big data computing with application-specific photonic network-on-chip architectures
In the era of big data, high performance data analytics applications are frequently executed
on large-scale cluster architectures to accomplish massive data-parallel computations …
on large-scale cluster architectures to accomplish massive data-parallel computations …
Universal wavelength reuse mechanism for optical networks-on-chip based on a cooperative game
H Yang, Y **e, T Song, Y Su, B Liu, J Chai… - Journal of Optical …, 2023 - opg.optica.org
Optical networks-on-chip (ONoCs) based on wavelength division multiplexing (WDM)
technology have lower end-to-end (ETE) delay, larger bandwidth, and higher throughput …
technology have lower end-to-end (ETE) delay, larger bandwidth, and higher throughput …
Chip temperature optimization for dark silicon many-core systems
In the dark silicon era, a fundamental problem is given a real-time computation demand,
how to determine if an on-chip multiprocessor system is able to accept this demand and to …
how to determine if an on-chip multiprocessor system is able to accept this demand and to …