Three-dimensional (3D) integration of electronic chips has been advocated by both industry
and academia for many years. It is acknowledged as one of the most promising approaches …

Design-based equivalent scaling now bears much of the burden of continuing the
semiconductor industry's trajectory of Moore's-Law value scaling. In the future, reductions of …

Since the physical defects such as resistive open and leakage in through silicon vias (TSVs)
caused by immature manufacturing techniques tend to undermine the reliability and yield of …

In this paper, we develop tier partitioning strategy to mitigate back-end-of-line (BEOL)
interconnect delay degradation and cost issues in monolithic 3D ICs (M3D). First, we study …

Three-dimensional integrated circuits (3D ICs) experience die-to-die variations in addition to
the already challenging within-die variations. This adds an additional design complexity and …

In this paper we study power, performance, and cost (PPC) tradeoffs for 2-tier, gate-level, full-
chip GDS monolithic 3D ICs (M3D) built using a foundry-grade 7nm bulk FinFET technology …

In this paper, we present a comprehensive study on the impact of power delivery network
(PDN) on full-chip wirelength, routability, power, and thermal effects in gate-level monolithic …

In advanced technology nodes, emerging 3-D integration technology is a promising “More
Than Moore” lever for continued scaling of system capability and value. In the 3-D integrated …

3DICs with multiple tiers are expected to achieve large benefits (eg, in terms of power, area)
as compared to conventional planar designs. However, few if any previous works study …

Over the past decade, CMOS scaling has seen increasingly intrusive challenges from cost,
variability, energy, reliability, and fundamental device-architectural and materials limitations …