Comprehensive review on electrical noise analysis of TFET structures
Abstract Tunnel Filed Effect Transistors (TFETs) have appeared as an alternative for
conventional CMOS due to their advantages like very low leakage current and steep sub …
conventional CMOS due to their advantages like very low leakage current and steep sub …
Sensitivity analysis on dielectric modulated Ge-source DMDG TFET based label-free biosensor
This work compares the performance of dielectric modulated (DM) based Ge-source dual
material double gate (DMDG) Tunnel Field Effect Transistor (TFET) and conventional (C) …
material double gate (DMDG) Tunnel Field Effect Transistor (TFET) and conventional (C) …
Ge-source based L-shaped tunnel field effect transistor for low power switching application
In this work, the performance of the heterojunction L-Tunnel Field Effect Transistor (LTFET)
has been analyzed with different engineering techniques such as bandgap engineering …
has been analyzed with different engineering techniques such as bandgap engineering …
Impact of back gate-drain overlap on DC and analog/HF performance of a ferroelectric negative capacitance double gate TFET
In this manuscript, we present a negative capacitance TFET with extended back gate-drain
overlap (DEBG-NC-TFET) to enhance DC and analog/high frequency (HF) performance …
overlap (DEBG-NC-TFET) to enhance DC and analog/high frequency (HF) performance …
Effect of asymmetric gate–drain overlap on ambipolar behavior of double-gate TFET and its impact on HF performances
To remove simultaneously the ambipolar conduction and enhance HF performances, we
propose a promising configuration of DG-TFET with asymmetric gate–drain overlap (ASGDO …
propose a promising configuration of DG-TFET with asymmetric gate–drain overlap (ASGDO …
Temperature analysis of Ge/Si heterojunction SOI-tunnel FET
Temperature is a thermal parameter which affects the device performance. This paper
presents the impact of the temperature variation on the electrical characteristics such as …
presents the impact of the temperature variation on the electrical characteristics such as …
Effect of scaling on noise in circular gate TFET and its application as a digital inverter
This paper reports the analysis of noise in Circular Gate TFET in presence of interface traps
(Gaussian) when the device is subjected to scaling of gate-drain underlap length and body …
(Gaussian) when the device is subjected to scaling of gate-drain underlap length and body …
Two-dimensional analytical modeling for electrical characteristics of Ge/Si SOI-tunnel FinFETs
This paper reports a two-dimensional (2-D) analytical model for surface potential, electric
field, drain current and threshold voltage of a three-dimensional (3-D) Ge/Si heterojunction …
field, drain current and threshold voltage of a three-dimensional (3-D) Ge/Si heterojunction …
Electrical noise in circular gate tunnel FET in presence of interface traps
This paper presents a novel architecture of Tunnel Field Effect Transistor (TFET) with a
circular gate and reports the effect of electrical noise on the device by comparing the results …
circular gate and reports the effect of electrical noise on the device by comparing the results …
An efficient ultra-low-power and superior performance design of ternary half adder using CNFET and gate-overlap TFET devices
S Vidhyadharan, SS Dan - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
This paper presents a novel ultra-low power yet high-performance device and circuit design
paradigm for implementing ternary logic based circuits using Gate-Overlap Tunnel FETs …
paradigm for implementing ternary logic based circuits using Gate-Overlap Tunnel FETs …