Heterogeneous reconfigurable systems provide drastically higher performance and lower
power consumption than traditional CPU-centric systems. Moreover, they do it at much lower …

Research on High-Level Synthesis has mainly focused on applications with statically
determinable characteristics and current tools often perform poorly in presence of data …

Abstract {This paper presents a new optimization technique called architectural retiming
which is able to improve the performance of many latency-constrained circuits. Architectural …

In this paper we present a satisfiability-based approach to the scheduling problem in high-
level synthesis. We formulate the resource constrained scheduling as a satisfiability (SAT) …

This paper presents global high-level synthesis (HLS) approach which addresses the
problem of synthesis of conditional behaviors under resource constraints. In proposed …

We present an automata model which concisely captures the constraints imposed by a data-
path, such as bus hazards, register constraints, and control encoding limitations. A set of …

A tool for the switch-level fault simulation and test evaluationof switched-capacitor systems is
presented. Time or frequency-domainfault simulations with SWITCAP and time-domain …

In high-level hardware synthesis (HLS), there is a gap in the quality of the synthesized
results between data-flow and control-flow dominated behavioral descriptions. Heuristics …

Optimization of hardware resources for conditional data-flow graph behavior is particularly
important when conditional behavior occurs in cyclic loops and maximization of throughput …

Conditional resource sharing has been identified as a possibility for optimizing high-level
synthesis results. We propose a hierarchical conditional dependency graph representation …