Escalating system-on-chip design complexity is pushing the design community to raise the
level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of …

In this paper, image processing algorithms designed in Zynq SoC using the Vivado HLS tool
are presented and compared with hand-coded designs. In Vivado HLS, the designer has the …

Using the example of a Reed–Solomon decoder, we provide insights into what type of
hardware structures are needed to be generated to achieve specific performance targets …

Today, one of the problems the scientific community is called upon to tackle is the well-
known von Neumann bottleneck, which concerns the limitation in the bandwidth between …

This paper presents a concept for automated architecture synthesis for adaptive
multiprocessors on chip, in particular for Field-Programmable Gate-Array (FPGA) devices …

Embedded hardware designs and their automation improve energy and engineering
efficiency. However, these two goals are often contradictory. The attempts to improve energy …

This paper is a continuation of a previous work by the same authors concerning the use of
automated high-level synthesis tools for obtaining high-performance FPGA implementations …

The development of state-of-the-art wireless communication transceivers in semiconductor
technology is a challenging process due to complexity and stringent requirements of modern …

New generation space-borne SAR (synthetic aperture radar) systems require high real-time
processing performance and have size, weight and power constrains. This paper presents a …

Computer simulation of switching power converters is complicated by the discontinuous
(switching) nature of the converter waveforms. When switching details of the waveform are of …