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A low active leakage and high reliability phase change memory (PCM) based non-volatile FPGA storage element
The high leakage current has been one of the critical issues in SRAM-based Field
Programmable Gate Arrays (FPGAs). In recent works, resistive non-volatile memories …
Programmable Gate Arrays (FPGAs). In recent works, resistive non-volatile memories …
Considerations for static energy reduction in digital CMOS ICs using NEMS power gating
S Sankar, US Kumar, M Goel… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
Due to its infinite OFF resistance, Nano-Electro-Mechanical Switches (NEMS) have been
recently proposed to reduce leakage current during the standby mode in large-scale Digital …
recently proposed to reduce leakage current during the standby mode in large-scale Digital …
Adaptive power gating of 32-bit Kogge Stone adder
AE Shapiro, F Atallah, K Kim, J Jeong, J Fischer… - Integration, 2016 - Elsevier
Static power consumes a significant portion of the available power budget. Consequently,
leakage current reduction techniques such as power gating have become necessary …
leakage current reduction techniques such as power gating have become necessary …
Multi-pole NEM relays and multiple-bits-per-cell RRAM for efficient 3-D ICs
A Levy - 2024 - search.proquest.com
In this dissertation, I present techniques for improving the power, performance, and area of
integrated circuits (ICs) through 3-D integration of two emerging nanotechnologies:(1) …
integrated circuits (ICs) through 3-D integration of two emerging nanotechnologies:(1) …
Stand-by power reduction using experimentally demonstrated nano-electromechanical switch in CMOS technologies
In this article, we demonstrate a double-clamped nano-electromechanical switch (NEMS)
with low stand-by power as an effective solution to the leakage issues in scaled CMOS …
with low stand-by power as an effective solution to the leakage issues in scaled CMOS …
3D integrated CMOS-NEM systems: Enabling next-generation computing technology
The emergence of the Internet of Things (IoT) has brought energy efficiency and functionality
to the forefront of challenges for future integrated circuits (chips). This necessitates …
to the forefront of challenges for future integrated circuits (chips). This necessitates …
Design of a temperature-aware low-voltage SRAM with self-adjustable sensing margin enhancement for high-temperature applications up to 300° C
This paper presents an 8-Kbit low-power SRAM for high-temperature (up to 300° C)
applications. For reliable low-voltage operation, we employed a decoupled 8T SRAM cell …
applications. For reliable low-voltage operation, we employed a decoupled 8T SRAM cell …
A New Physical Design Flow for a Selective State Retention Based Approach
J Rabinowicz, S Greenberg - Journal of Low Power Electronics and …, 2021 - mdpi.com
This research presents a novel approach for physical design implementation aimed for a
System on Chip (SoC) based on Selective State Retention techniques. Leakage current has …
System on Chip (SoC) based on Selective State Retention techniques. Leakage current has …
Pull-in voltage and fabrication yield analysis of all-metal-based nanoelectromechanical switches
We designed a one-mask process for all-molybdenum-based laterally actuated
nanoelectromechanical switches. The damascene-like process is designed to ensure a …
nanoelectromechanical switches. The damascene-like process is designed to ensure a …
A low power localized 2T1R STT-MRAM array with pipelined quad-phase saving scheme for zero sleep power systems
The high leakage power due to process nodes scaling down has been one of the critical
issues in CMOS circuits, especially the sleep power critical systems. The conventional …
issues in CMOS circuits, especially the sleep power critical systems. The conventional …