Multi-core devices are envisioned to support the development of next-generation safety-
critical systems, enabling the on-chip integration of functions of different criticality. This …

With the continued success of the open RISC-V architecture, practical deployment of RISC-V
processors necessitates an in-depth consideration of their testability, safety and security …

This paper presents a dual-core lockstep (DCLS) implementation to protect hard-core
processors against radiation-induced soft errors. The proposed DCLS is applied to an …

The Arm Triple Core Lock-Step (TCLS) architecture is the natural evolution of Arm Cortex-R
Dual Core Lock-Step (DCLS) processors to increase dependability, predictability, and …

Safety and resilience are critical for autonomous unmanned aerial vehicles (UAVs). We
introduce MAVFI, the micro aerial vehicles (MAVs) resilience analysis methodology to …

High-Performance Computing (HPC) platforms become a must in automotive systems to
enable autonomous driving. However, automotive platforms must avoid Common Cause …

Autonomous Driving (AD) imposes the use of high-performance hardware, such as GPUs, to
perform object recognition and tracking in real-time. However, differently to the consumer …

The shrinking of technology nodes allows higher performance, but susceptibility to soft
errors increases. The protection has been implemented mainly by lockstep or hardened …

Safety-related systems, such as those in automotive, avionics and space, impose the
existence of appropriate safety measures to meet the safety requirements of the system. In …

Microcontrollers running safety-critical applications with high integrity requirements must
provide appropriate safety measures to manage random hardware faults. For instance …