Porous dielectrics in microelectronic wiring applications
V McGahay - Materials, 2010 - mdpi.com
Porous insulators are utilized in the wiring structure of microelectronic devices as a means of
reducing, through low dielectric permittivity, power consumption and signal delay in …
reducing, through low dielectric permittivity, power consumption and signal delay in …
Superior mechanical properties of dense and porous organic/inorganic hybrid thin films
The intrinsic mechanical properties of a given material strongly depend upon its chemical
nature: the organics tend to be soft, but tough, while the inorganic materials are hard but …
nature: the organics tend to be soft, but tough, while the inorganic materials are hard but …
Structure and method of chemically formed anchored metallic vias
SC Mehta, DC Edelstein, JA Fitzsimmons… - US Patent …, 2009 - Google Patents
Methods are provided that enable the ability to use a less aggressive liner processes, while
producing structures known to give a desired high stress migration and electro-migration …
producing structures known to give a desired high stress migration and electro-migration …
[HTML][HTML] Delamination in patterned films
When the dielectric constant of an insulator in an interconnect is reduced, mechanical
properties are often compromised, giving rise to significant challenges in interconnect …
properties are often compromised, giving rise to significant challenges in interconnect …
Via resistance reduction in advanced copper interconnects
CC Yang, T Spooner, P McLaughlin… - IEEE Electron …, 2016 - ieeexplore.ieee.org
Via resistance reduction in Cu interconnects was achieved through a pre-liner dielectric
nitridation process prior to pure Ta liner deposition. Replacing TaN with Ta in the …
nitridation process prior to pure Ta liner deposition. Replacing TaN with Ta in the …
Measurement of back end of line thermal resistance for 3D chip stacks
EG Colgan, RJ Polastre… - 29th IEEE …, 2013 - ieeexplore.ieee.org
The thermal resistances of thirty-nine different back end of line (BEOL) test sites consisting of
four line levels and three via levels in SiCOH were measured. The measured unit resistance …
four line levels and three via levels in SiCOH were measured. The measured unit resistance …
A 45 nm CMOS node Cu/Low-k/Ultra Low-k PECVD SiCOH (k= 2.4) BEOL technology
S Sankaran, S Arai, R Augur, M Beck… - 2006 International …, 2006 - ieeexplore.ieee.org
A high performance 45nm BEOL technology with proven reliability is presented. This BEOL
has a hierarchical architecture with up to 10 wiring levels with 5 in PECVD SiCOH (k= 3.0) …
has a hierarchical architecture with up to 10 wiring levels with 5 in PECVD SiCOH (k= 3.0) …
Nanoindentation analysis of mechanical properties of low to ultralow dielectric constant SiCOH films
Carbon-doped oxide SiCOH films with low to ultralow dielectric constants were prepared on
a Si substrate by plasma-enhanced chemical vapor deposition (PECVD) from mixtures of …
a Si substrate by plasma-enhanced chemical vapor deposition (PECVD) from mixtures of …
Reliability Challenges in Copper Metallizations arising with the PVD Resputter Liner Engineering for 65nm and beyond
AH Fischer, O Aubel, J Gill, TC Lee, B Li… - 2007 IEEE …, 2007 - ieeexplore.ieee.org
In this paper the influence of liner deposition parameters on the reliability of 65nm copper
metallizations have been investigated for two different deposition sequences. The use of …
metallizations have been investigated for two different deposition sequences. The use of …
Stress migration lifetime for Cu interconnects with CoWP-only cap
JP Gambino, CL Johnson, JE Therrien… - … on Device and …, 2006 - ieeexplore.ieee.org
Stress migration lifetime is characterized for a CoWP-only cap process (ie, no dielectric cap)
and a CoWP+ SiN cap process. For the CoWP-only process, the stress migration lifetime …
and a CoWP+ SiN cap process. For the CoWP-only process, the stress migration lifetime …