Nonvolatile memory device having a vertical structure and a memory system including the same
BS Lim, JY Kim, SW Shim, I Park - US Patent 10,672,791, 2020 - Google Patents
A nonvolatile memory device including: a first semiconductor layer including word lines, bit
lines, first and second upper substrates adjacent to each other and a memory cell array …
lines, first and second upper substrates adjacent to each other and a memory cell array …
Semiconductor memory device
H Miyagawa, R Takaishi, T Numata - US Patent 10,367,054, 2019 - Google Patents
A semiconductor memory device according to an embodiment comprises a plurality of
control gate electrodes, a first semiconductor layer, and a gate insulating layer. The plurality …
control gate electrodes, a first semiconductor layer, and a gate insulating layer. The plurality …
Nonvolatile memory device having a vertical structure and a memory system including the same
BS Lim, JY Kim, SW Shim, I Park - US Patent 11,211,403, 2021 - Google Patents
(57) ABSTRACT A nonvolatile memory device including: a first semiconduc tor layer
comprising a plurality of first word lines extending in a first direction, a first upper substrate …
comprising a plurality of first word lines extending in a first direction, a first upper substrate …
Nonvolatile memory device having a vertical structure and a memory system including the same
BS Lim, JY Kim, SW Shim, I Park - US Patent 10,978,481, 2021 - Google Patents
A nonvolatile memory device including: a first semiconduc tor layer including word lines, bit
lines, first and second upper substrates adjacent to each other and a memory cell array …
lines, first and second upper substrates adjacent to each other and a memory cell array …
Semiconductor device and manufacturing method of semiconductor device
YH Noh - US Patent 11,495,473, 2022 - Google Patents
A method of manufacturing a semiconductor device includes forming a stacked structure
with first material layers and second material layers that are stacked alternately with each …
with first material layers and second material layers that are stacked alternately with each …
Semiconductor device including a cutting region having a height greater than a height of a channel structure
GW Lim, SC Baek, JS Cheon, JW Shin… - US Patent …, 2023 - Google Patents
A semiconductor device includes a peripheral circuit region on a lower substrate, and
including circuit elements, memory cell regions including memory cells on each of a first …
including circuit elements, memory cell regions including memory cells on each of a first …
Nonvolatile memory device having a vertical structure and a memory system including the same
BS Lim, JY Kim, SW Shim, I Park - US Patent 11,233,068, 2022 - Google Patents
(57) ABSTRACT A nonvolatile memory device including: a first semiconduc tor layer
including word lines, bit lines, first and second upper substrates adjacent to each other and …
including word lines, bit lines, first and second upper substrates adjacent to each other and …
Vertical memory devices
K Yun, C Kim, D Kang - US Patent 11,430,804, 2022 - Google Patents
A vertical memory device is provided. The vertical memory device includes gate electrodes
formed on a substrate and spaced apart from each other in a first direction substantially …
formed on a substrate and spaced apart from each other in a first direction substantially …
Semiconductor memory device including a pillar-shaped channel penetrating a stacked body
S Hazue - US Patent 10,818,686, 2020 - Google Patents
According to one embodiment, a semiconductor memory device includes: a substrate; a first
conductive layer arranged above the substrate; a stacked body arranged on the first …
conductive layer arranged above the substrate; a stacked body arranged on the first …