In recent years, physical unclonable functions (PUFs) have gained a lot of attention as
mechanisms for hardware-rooted device authentication. While the majority of the previously …

Aggressive technology scaling and increased static and dynamic variability caused by
process, temperature, voltage, and aging effects make nanometer circuits prone to timing …

Voltage over-scaling (VoS) may be one of the most effective power reduction approaches,
however, it makes circuits susceptible to timing failures. Various techniques were proposed …

The increased variability and adopted low supply voltages render nanometer devices prone
to timing failures, which threaten the functionality of digital circuits. Recent schemes focused …

To meet the security requirements of resource-constrained systems, a software PUF (SPUF)
scheme based on the encryption algorithm is proposed using the timing violation to …

The increased variability renders nanometer devices prone to timing errors. Recent work
focused on the development of error prediction models for either evaluating the effects of …

In 1975, Moore observed that the complexity of integrated circuits would double every two
years towards the end of the decade, instead of every year [83]. He predicted that this would …

When it comes to decreasing margins and increasing energy efficiency in near-threshold
and sub-threshold processors, timing error resilience may be viewed as a potentially …

In 1975, Moore wrote regarding the semiconductor complexity curve [140]:" The new slope
might approximate a doubling every two years, rather than every year, by the end of the …

In the past two decades approximation techniques have been applied at the circuit and
microarchitecture level for exploiting the error-resilient nature of many applications. The …