Physically based models of electromigration: From Black's equation to modern TCAD models

RL De Orio, H Ceric, S Selberherr - Microelectronics Reliability, 2010 - Elsevier
Electromigration failure is a major reliability concern for integrated circuits. The continuous
shrinking of metal line dimensions together with the interconnect structure arranged in many …

Resistance increase due to electromigration induced depletion under TSV

T Frank, C Chappaz, P Leduc, L Arnaud… - 2011 International …, 2011 - ieeexplore.ieee.org
Resistance increase due to electromigration induced depletion under TSV Page 1 Resistance
increase due to electromigration induced depletion under TSV T. Frank1,3, C. Chappaz1, P …

Redundancy-aware electromigration checking for mesh power grids

S Chatterjee, M Fawaz, FN Najm - 2013 IEEE/ACM …, 2013 - ieeexplore.ieee.org
Electromigration (EM) is re-emerging as a significant problem in modern integrated circuits
(IC). Especially in power grids, due to shrinking wire widths and increasing current densities …

Assessment of critical Co electromigration parameters

OV Pedreira, M Lofrano… - 2022 IEEE …, 2022 - ieeexplore.ieee.org
We perform a detailed assessment of the electromigration performance of Co interconnects.
Package level EM measurements were performed during> 11 months. Our estimate of the …

Energy-efficient and reliable 3D Network-on-Chip (NoC): Architectures and optimization algorithms

S Das, JR Doppa, PP Pande… - 2016 IEEE/ACM …, 2016 - ieeexplore.ieee.org
The Network-on-Chip (NoC) paradigm has emerged as an enabler for integrating a large
number of embedded cores in a single die. Three-dimensional (3D) integration, a …

[HTML][HTML] Electromigration failure in a copper dual-damascene structure with a through silicon via

RL de Orio, H Ceric, S Selberherr - Microelectronics Reliability, 2012 - Elsevier
Electromigration induced failure development in a copper dual-damascene structure with a
through silicon via (TSV) located at the cathode end of the line is studied. The resistance …

[HTML][HTML] A compact model for early electromigration failures of copper dual-damascene interconnects

RL De Orio, H Ceric, S Selberherr - Microelectronics Reliability, 2011 - Elsevier
A compact model for early electromigration failures in copper dual-damascene interconnects
is proposed. The model is based on the combination of a complete void nucleation model …

Stress-aware periodic test of interconnects

S Sadeghi-Kohan, S Hellebrand… - Journal of Electronic …, 2021 - Springer
Safety-critical systems have to follow extremely high dependability requirements as
specified in the standards for automotive, air, and space applications. The required high fault …

Making a case for partially connected 3D NoC: NFIC versus TSV

AI Arka, S Gopal, JR Doppa, D Heo… - ACM Journal on Emerging …, 2020 - dl.acm.org
3D Network-on-Chip (3D NoC) enables design of high-performance and energy-efficient
manycore computing platforms. Two of the commonly used vertical interconnection …

Workload-aware periodic interconnect BIST

S Sadeghi-Kohan, S Hellebrand… - IEEE Design & …, 2023 - ieeexplore.ieee.org
Workload-Aware Periodic Interconnect BIST Page 1 Workload-Aware Periodic Interconnect
BIST Somayeh Sadeghi-Kohan1, Sybille Hellebrand1, Hans-Joachim Wunderlich2 …