[BOOK][B] System-on-chip test architectures: nanometer design for testability
LT Wang, CE Stroud, NA Touba - 2010 - books.google.com
Modern electronics testing has a legacy of more than 40 years. The introduction of new
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
A set of benchmarks for modular testing of SOCs
EJ Marinissen, V Iyengar… - Proceedings …, 2002 - ieeexplore.ieee.org
This paper presents the ITC'02 SOC test benchmarks. The purpose of this new benchmark
set is to stimulate research into new methods and tools for modular testing of SOCs and to …
set is to stimulate research into new methods and tools for modular testing of SOCs and to …
Enhanced regeneration of phosphorus during formation of the most recent eastern Mediterranean sapropel (S1)
Phosphorus regeneration and burial fluxes during and after formation of the most recent
sapropel S1 were determined for two deep-basin, low-sedimentation sites in the eastern …
sapropel S1 were determined for two deep-basin, low-sedimentation sites in the eastern …
System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints
V Iyengar, K Chakrabarty - IEEE transactions on computer …, 2002 - ieeexplore.ieee.org
Test scheduling is an important problem in system-on-a-chip (SOC) test automation. Efficient
test schedules minimize the overall system test application time, avoid test resource …
test schedules minimize the overall system test application time, avoid test resource …
[BOOK][B] Power-constrained testing of VLSI circuits
N Nicolici, B Al-Hashimi - 2003 - Springer
Increased levels of chip integration combined with physical limitations of heat removal
devices, cooling mechanisms and battery capacity, have established energy-efficiency as an …
devices, cooling mechanisms and battery capacity, have established energy-efficiency as an …
An integrated framework for the design and optimization of SOC test solutions
We propose an integrated framework for the design of SOC test solutions, which includes a
set of algorithms for early design space exploration as well as extensive optimization for the …
set of algorithms for early design space exploration as well as extensive optimization for the …
An integrated system-on-chip test framework
In this paper we propose a framework for the testing of system-on-chip (SOC), which
includes a set of design algorithms to deal with test scheduling, test access mechanism …
includes a set of design algorithms to deal with test scheduling, test access mechanism …
Efficient test solutions for core-based designs
E Larsson - Introduction to Advanced System-on-Chip Test Design …, 2005 - Springer
A test solution for a complex system requires the design of a test access mechanism (TAM),
which is used for the test data transportation, and a test schedule of the test data …
which is used for the test data transportation, and a test schedule of the test data …
[BOOK][B] Introduction to advanced system-on-chip test design and optimization
E Larsson - 2006 - books.google.com
Testing of Integrated Circuits is important to ensure the production of fault-free chips.
However, testing is becoming cumbersome and expensive due to the increasing complexity …
However, testing is becoming cumbersome and expensive due to the increasing complexity …
Thermal-safe test scheduling for core-based system-on-chip integrated circuits
P Rosinger, BM Al-Hashimi… - IEEE Transactions on …, 2006 - ieeexplore.ieee.org
Overheating has been acknowledged as a major problem during the testing of complex
system-on-chip integrated circuits. Several power-constrained test-scheduling solutions …
system-on-chip integrated circuits. Several power-constrained test-scheduling solutions …