Thispaperpresents two new algorithms, Redundant VectorElimination (RVE) and Essential
Fault Reduction (EFR), for generating compact test setsfor combinational circuits under the …

The rapid development of online social networks not only enables prompt and convenient
dissemination of desirable information but also incurs fast and wide propagation of …

A novel test vector compression/decompression technique is proposed for reducing the
amount of test data that must be stored on a tester and transferred to each core when testing …

Aims: To clarify the decision-making and bereavement needs of family members who had
organ donation discussed with them; to provide a rationale for further preparation of …

Test set compaction for combinational circuits is studied in this paper. Two active
compaction methods based on essential faults are developed to reduce a given test set. The …

Recently a deterministic built-in self-test scheme has been presented based on reseeding of
multiple-polynomial linear feedback shift registers. This scheme encodes deterministic test …

Given a test set for stuck-at faults of a combinational circuit or a full-scan sequential circuit,
some of the primary input values may be changed to the opposite logic values without losing …

Design-for-testability (DFT) for synchronous sequential circuits allows the generation and
application of tests that rely on non-functional operation of the circuit. This can result in …

Automatic Test Pattern Generation (ATPG) based on Boolean Satisfiability (SAT) is a robust
alternative to classical structural ATPG. Due to the powerful reasoning engines of modern …

A static compaction procedure to reduce test set size for scan designs and a procedure to
order test patterns in order to steepen the fault coverage curve are presented. The …