With the down-scaling of CMOS technology, the design complexity of very large-scale
integrated is increasing. Although the application of machine learning (ML) techniques in …

The year 2011 marked an important transition for FPGA high-level synthesis (HLS), as it
went from prototy** to deployment. A decade later, in this article, we assess the progress …

Sparse linear algebra operators are memory bound due to low compute to memory access
ratio and irregular data access patterns. The exceptional bandwidth improvement provided …

With the pursuit of improving compute performance under strict power constraints, there is
an increasing need for deploying applications to heterogeneous hardware architectures with …

While high-level synthesis (HLS) offers sophisticated techniques to optimize designs for
area and performance, HLS-estimated resource usage and timing often deviate significantly …

FPGAs require a much longer compilation cycle than conventional computing platforms like
CPUs. In this paper, we shorten the overall compilation time by co-optimizing the HLS …

The emergence of High-Level Synthesis (HLS) tools shifted the paradigm of hardware
design by making the process of map** high-level programming languages to hardware …

Hardware accelerators based on field programmable gate array (FPGA) and system on chip
(SoC) devices have gained attention in recent years. One of the main reasons is that these …

To achieve high performance with FPGA-equipped heterogeneous compute systems, it is
crucial to co-optimize data placement and compute scheduling to maximize data reuse and …

FPGAs are now used in public clouds to accelerate a wide range of applications, including
many that operate on sensitive data such as financial and medical records. We present …