A review of recent research on heat transfer in three-dimensional integrated circuits (3-D ICs)
Three-dimensional integrated circuits (3-D IC) technology has emerged in the past few
decades, driven in part by the techno-economic difficulties of dimensional scaling and the …
decades, driven in part by the techno-economic difficulties of dimensional scaling and the …
Wafer-level Cu–Cu bonding technology
YS Tang, YJ Chang, KN Chen - Microelectronics Reliability, 2012 - Elsevier
Semiconductor industry currently utilizes copper wafer bonding as one of key technologies
for 3D integration. This review paper describes both science and technology of copper wafer …
for 3D integration. This review paper describes both science and technology of copper wafer …
3-D hyperintegration and packaging technologies for micro-nano systems
JQ Lu - Proceedings of the IEEE, 2009 - ieeexplore.ieee.org
Three-dimensional (3-D) hyperintegration is an emerging technology, which vertically stacks
and interconnects multiple materials, technologies, and functional components to form …
and interconnects multiple materials, technologies, and functional components to form …
[ЦИТИРОВАНИЕ][C] Microelectronic applications of chemical mechanical planarization
Y Li - 2007 - books.google.com
An authoritative, systematic, and comprehensive description of current CMP technology
Chemical Mechanical Planarization (CMP) provides the greatest degree of planarization of …
Chemical Mechanical Planarization (CMP) provides the greatest degree of planarization of …
Semiconductor substrates with unitary vias and via terminals, and associated systems and methods
KK Kirby, KR Parekh - US Patent 8,030,780, 2011 - Google Patents
BACKGROUND Packaged semiconductor dies, including memory chips, microprocessor
chips, and imager chips, typically include a semiconductor die mounted to a Substrate and …
chips, and imager chips, typically include a semiconductor die mounted to a Substrate and …
Wafer-level 3D integration technology
SJ Koester, AM Young, RR Yu… - IBM Journal of …, 2008 - ieeexplore.ieee.org
An overview of wafer-level three-dimensional (3D) integration technology is provided. The
basic reasoning for pursuing 3D integration is presented, followed by a description of the …
basic reasoning for pursuing 3D integration is presented, followed by a description of the …
Analytical and numerical modeling of the thermal performance of three-dimensional integrated circuits
A Jain, RE Jones, R Chatterjee… - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
Three-dimensional (3D) interconnection technology offers several electrical advantages,
including reduced signal delay, reduced interconnect power, and design flexibility. 3D …
including reduced signal delay, reduced interconnect power, and design flexibility. 3D …
A study of thermo-mechanical stress and its impact on through-silicon vias
N Ranganathan, K Prasad… - Journal of …, 2008 - iopscience.iop.org
The BOSCH etch process, which is commonly used in microelectromechanical system
fabrication, has been extensively investigated in this work for implementation in through …
fabrication, has been extensively investigated in this work for implementation in through …
Wafer-level heterogeneous integration for MOEMS, MEMS, and NEMS
Wafer-level heterogeneous integration technologies for microoptoelectromechanical
systems (MOEMS), microelectromechanical systems (MEMS), and nanoelectromechanical …
systems (MOEMS), microelectromechanical systems (MEMS), and nanoelectromechanical …
Is 3D chip technology the next growth engine for performance improvement?
PG Emma, E Kursun - IBM journal of research and development, 2008 - ieeexplore.ieee.org
The semiconductor industry is reaching a fascinating confluence in several evolutionary
trends that will likely lead to a number of revolutionary changes in how computer systems …
trends that will likely lead to a number of revolutionary changes in how computer systems …