Review of neural network model acceleration techniques based on FPGA platforms

F Liu, H Li, W Hu, Y He - Neurocomputing, 2024 - Elsevier
Neural network models, celebrated for their outstanding scalability and computational
capabilities, have demonstrated remarkable performance across various fields such as …

High-level synthesis design space exploration: Past, present, and future

BC Schafer, Z Wang - … on Computer-Aided Design of Integrated …, 2019 - ieeexplore.ieee.org
This article presents a survey of the different modern high-level synthesis (HLS) design
space exploration (DSE) techniques that have been proposed so far to automatically …

Pylog: An algorithm-centric python-based FPGA programming and synthesis flow

S Huang, K Wu, H Jeong, C Wang… - IEEE Transactions …, 2021 - ieeexplore.ieee.org
The exploding complexity and computation efficiency requirements of applications are
stimulating a strong demand for hardware acceleration with heterogeneous platforms such …

High-level synthesis performance prediction using gnns: Benchmarking, modeling, and advancing

N Wu, H Yang, Y **e, P Li, C Hao - Proceedings of the 59th ACM/IEEE …, 2022 - dl.acm.org
Agile hardware development requires fast and accurate circuit quality evaluation from early
design stages. Existing work of high-level synthesis (HLS) performance prediction usually …

Accelerating framework of transformer by hardware design and model compression co-optimization

P Qi, EHM Sha, Q Zhuge, H Peng… - 2021 IEEE/ACM …, 2021 - ieeexplore.ieee.org
State-of-the-art Transformer-based models, with gigantic parameters, are difficult to be
accommodated on resource constrained embedded devices. Moreover, with the …

High-level synthesis hardware design for fpga-based accelerators: Models, methodologies, and frameworks

RS Molina, V Gil-Costa, ML Crespo, G Ramponi - IEEE Access, 2022 - ieeexplore.ieee.org
Hardware accelerators based on field programmable gate array (FPGA) and system on chip
(SoC) devices have gained attention in recent years. One of the main reasons is that these …

Correlated multi-objective multi-fidelity optimization for HLS directives design

Q Sun, T Chen, S Liu, J Chen, H Yu, B Yu - ACM Transactions on Design …, 2022 - dl.acm.org
High-level synthesis (HLS) tools have gained great attention in recent years because it
emancipates engineers from the complicated and heavy hardware description language …

Ai-assisted synthesis in next generation eda: Promises, challenges, and prospects

N Wu, Y **e, C Hao - 2022 IEEE 40th International Conference …, 2022 - ieeexplore.ieee.org
Despite the great advance achieved by electronic design automation (EDA) tools, there is
still a long way towards hardware agile development, whose ultimate goal is to reduce chip …

FAMOUS: Flexible Accelerator for the Attention Mechanism of Transformer on UltraScale+ FPGAs

E Kabir, MA Kabir, ARJ Downey, JD Bakos… - arxiv preprint arxiv …, 2024 - arxiv.org
Transformer neural networks (TNNs) are being applied across a widening range of
application domains, including natural language processing (NLP), machine translation, and …

FP-Stereo: Hardware-efficient stereo vision for embedded applications

J Zhao, T Liang, L Feng, W Ding… - … Conference on Field …, 2020 - ieeexplore.ieee.org
Fast and accurate depth estimation, or stereo matching, is essential in embedded stereo
vision systems, requiring substantial design effort to achieve an appropriate balance among …