Hardware verification of modern electronic systems has been identified as a major
bottleneck due to the increasing complexity and time-to-market constraints. One of the major …

We present GoldMine, a methodology for generating assertions automatically in hardware.
Our method involves a combination of data mining and static analysis of the register transfer …

Several approaches exist for specification mining of hardware designs. Most of them work at
RTL and they extract assertions in the form of temporal relations between Boolean variables …

With the ever-increasing hardware design complexity comes the realization that efforts
required for hardware verification increase at an even faster rate. Driven by the push from …

This article presents HARM, a tool to generate linear temporal logic (LTL) assertions starting
from a set of user-defined hints and the simulation traces of the design under verification …

The continuing increase in functional requirements of modern hardware designs means the
traditional functional verification process becomes inefficient in meeting the time-to-market …

Isadora is a methodology for creating information flow specifications of hardware designs.
The methodology combines information flow tracking and specification mining to produce a …

Isadora is a specification mining tool for creating information-flow properties for hardware.
Isadora combines hardware information-flow tracking and specification mining to produce …

Mathematical word problems (MWP) test critical aspects of reading comprehension in
conjunction with generating a solution that agrees with the “story” in the problem. In this …

This paper presents UNDINE, a tool to automatically generate security critical Linear
Temporal Logic (LTL) properties of processor architectures. UNDINE handles complex …